Serially accessed semiconductor memory with tapped shift registe

Details Serially accessed semiconductor memory with tapped shift registe Serially accessed semiconductor memory with tapped shift registe

1985-01-22

1987-05-19

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sequential

365189, 365221, G11C 800

Patent

active

046673130

ABSTRACT:
A semiconductor memory comprises four arrays (10), (12), (14) and (16) disposed on a single semiconductor chip. Each of the arrays has a serial shift register (86) associated therewith. Data is transferred from the bit lines of the associated array through a transfer gate (90) for storage in the shift register (86). A tap latch (88) is provided on the output of each of the shift bits in the shift register (86) for determining the output therefrom. The tap latch (88) stores a tap decode signal which is decoded from a tap address by the column decoder (30). The column decoder (30) also decodes the column address in the random mode. The tap decode signal selects any of the shift bits in the shift register (86).

REFERENCES:
patent: 3930239 (1975-12-01), Salters et al.
patent: 4322635 (1982-03-01), Redwine
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4347587 (1982-08-01), Rao
patent: 4541075 (1985-09-01), Dill et al.

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