Serializer/deserializer with a triangular matrix

Details Serializer/deserializer with a triangular matrix Serializer/deserializer with a triangular matrix

1991-01-25

1992-03-31

Williams, Howard L.

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

341101, 357 45, 365 51, 365219, H03M 900

Patent

active

051012022

ABSTRACT:
A serializer/deserializer for a flow of n-bits of data shifted according to the rate of a clock includes an n-rows and n-columns matrix of 1-bit registers (00-77). Each 1-bit register is connected through its input to a first switch connected to the output of the register in the same row and lower rank column and to a second switch connected to the output of the register in the same column and upper rank row. Input terminals (E0-E7) are connected to the registers of the lower rank column and of the upper rank row. Output terminals (S0-S7) are connected to the registers of the upper rank column and of the lower rank row. The matrix cells are arranged according to a triangle, the cells being arranged one with respect to the other according to the structural corresponding to folding a square matrix along its diagonal.

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Ruoff, IBM Technical Disclosure Bulletin, "Triangular Matrix Array", vol. 3, No. 5, Oct. 1960, p. 48.
Millman, Microelectronics Digital and Analog Circuits and Systems, 1979, McGraw-Hill, pp. 215, 219, 220.

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