Serialized difference flag circuit

Details Serialized difference flag circuit Serialized difference flag circuit

1992-06-22

1994-10-11

Wambach, Margaret R.

Communications: electrical

Digital comparator systems

307355, G06F 702

Patent

active

053551133

ABSTRACT:
Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status without the use of subtractor circuitry. Bit comparators, which together comprise a magnitude comparator, determine if a first bit is less than, equal to, or greater than a second bit, and operate to produce a composite comparator output. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. In addition, control of selected bits, such as the most significant bits (MSBs), of the numbers is included and may be used as necessary to avoid a wrap-around condition.

REFERENCES:
patent: 3196283 (1965-07-01), Flattau
patent: 3278761 (1966-10-01), Goyer
patent: 4935719 (1990-06-01), McClure
patent: 5027330 (1991-06-01), Miller
patent: 5084841 (1992-01-01), Williams et al.
J. Daniels "Circuits for fast binary attition" Electronic Engineering vol. 62, No. 760, Apr. 1990, London GB, pp. 27-28.

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