Serial transistor-cell array architecture

Static information storage and retrieval – Analog storage systems – Resistive

Reexamination Certificate

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C365S063000

Reexamination Certificate

active

10873112

ABSTRACT:
A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. Unique sensing techniques are provided to sense the states of the storage elements. The logical states of the storage elements are decoupled from one another and are read independently.

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