Static information storage and retrieval – Analog storage systems – Resistive
Reexamination Certificate
2006-12-12
2006-12-12
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Analog storage systems
Resistive
C365S100000, C365S148000
Reexamination Certificate
active
07149100
ABSTRACT:
A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells associated with an addressed cell to a known number having a sneak path resistance that can be calculated and taken into consideration when sensing the addressed memory cell. Blocks of memory cells are associated with access transistors, which separate the memory cells connected thereto into one half (½) sections of cell blocks. The access transistors can be associated with n memory cells, where n is an even number of at least 2; there may or may not be an equal number of cells on either side of the transistor. The memory array has memory cells, which are grouped into 1T-2nCell blocks.
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Dickstein & Shapiro LLP
Nguyen Tan T.
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