Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Patent
1991-11-26
1993-02-16
Hoff, Marc
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
341159, H03M 114
Patent
active
051874830
ABSTRACT:
A serial-to-parallel type A/D converter includes a resistance array, a plurality of comparators for upper bits, a plurality of comparators for lower bits, an encoder for upper bits, an encoder for lower bits and an adder. The resistance array divides a predetermined reference voltage to generate upper reference voltages, and by dividing the step width of the upper reference voltage, generates lower reference voltages. The plurality of comparators for the upper bits compare the analog input signal with the upper reference voltages, and applies the result of comparison to the encoder for the upper bits. The encoder for the upper bits calculates an estimated value of the upper bits based on the result of comparison, and select second reference voltages in the range provided by adding .+-.1/2 LSB to 1LSB corresponding to the estimated value of the upper bits. The plurality of comparators for the lower bits calculate the lower bits and a correcting bit based on the selected second reference voltages. The adder adds the correcting bit to the estimated value of the upper bits to correct the estimated value.
REFERENCES:
patent: 4533903 (1985-08-01), Yamada et al.
patent: 4559522 (1985-12-01), Sekino et al.
patent: 4599599 (1986-07-01), Sekino et al.
patent: 4903028 (1990-02-01), Fukushima
patent: 5019820 (1991-05-01), Matsuzawa et al.
"A 20 Hz 8 bit Half-Flash CMOS A/D Converter", ICD88-8, pp. 51-58.
Institute of Electronics, Information and Communication Engineers, 1989 Spring National Conference, pp. 5-396, 5-397.
Conlin David G.
Hoff Marc
O'Connell Robert F.
Sharp Kabushiki Kaisha
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