Serial to parallel converter enabled by multiplexed flip-flop co

Details Serial to parallel converter enabled by multiplexed flip-flop co Serial to parallel converter enabled by multiplexed flip-flop co

1998-03-23

2000-04-18

Young, Brian

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

341141, H03M 900

Patent

active

060520736

ABSTRACT:
A serial to parallel converter comprising a serial shift register for receiving an incoming serial stream of bits, a parallel word latch for receiving in parallel bits stored by the shift register, when enabled by an enable signal at an enable time, and for providing a parallel data output signal, a controller for generating an enable signal at the enable time and applying the enable signal to the parallel word latch, the controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

REFERENCES:
patent: 4408336 (1983-10-01), DasGupta
patent: 4584673 (1986-04-01), Kuijk
patent: 5249186 (1993-09-01), Remson
patent: 5686913 (1997-11-01), Coln et al.
patent: 5857005 (1999-01-01), Buckenmeier
patent: 5926120 (1999-07-01), Swenson et al.

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