Serial-to-parallel converter

Details Serial-to-parallel converter Serial-to-parallel converter

1999-08-03

2001-03-06

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

Reexamination Certificate

active

06198415

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a serial-to-parallel converter (SPC) for converting a serial signal with a predetermined bit rate into a parallel signal with a predetermined bit width.
A conventional SPC includes a shift register and a latch circuit. A shift register is made up of a plurality of flip-flops (FF) connected in series to each other. A serial signal with a predetermined bit rate is input to an initial-stage FF. In response to a common shift clock signal at a frequency matched with the bit rate of the serial signal, each FF operates to forward its input signal to an FF on the next stage. On the other hand, responsive to a latch clock signal at a frequency lower than that of the shift clock signal, the latch circuit latches the respective output signals of the FFs at a time, thereby outputting a parallel signal based on the results of latching.
In the conventional SPC, if the bit rate of the serial signal is very high, however, the shift register might operate erroneously. For example, if the bit rate of the serial signal is 1 Gbps, then each FF included in the shift register should operate at a very high speed in response to a shift clock signal with a frequency as high as 1 GHz. Accordingly, it is difficult to prevent the shift register from operating erroneously.
SUMMARY OF THE INVENTION
An object of the present invention is providing a highly reliable SPC that can operate at a high speed without using a shift register.
To achieve this object, the present invention uses a voltage controlled oscillator (VCO) included in a phase locked loop (PLL), connects a plurality of delay devices associated with the VCO in series to each other, and inputs a serial signal to an initial-stage one of the delay devices.
Specifically, an SPC according to the present invention includes a PLL, a delay circuit and a latch circuit. The PLL includes: a VCO having a plurality of logical elements connected together in a ring; and a phase detector for supplying a control voltage to each of these logical elements of the VCO to control the oscillation frequency of the VCO. The control voltage is defined based on a phase difference between a reference clock signal and an oscillation signal of the VCO. The delay circuit is made up of a plurality of delay devices connected in series to each other. A delay caused by each of these delay devices is controlled with the same voltage as the control voltage applied to the VCO. The serial signal is input to an initial-stage one of these delay devices. The latch circuit latches part or all of the output signals of the delay devices of the delay circuit in response to a latch clock signal and outputs a parallel signal based on a result of latching.
These delay devices, each causing just a short delay, are easily implementable. In addition, it is not necessary to supply a shift clock signal to these delay devices. According to the present invention, the delay caused by each of these delay devices can be precisely controlled with the same voltage as the control voltage applied to each of the logical elements in the VCO.


REFERENCES:
patent: 6052073 (2000-04-01), Carr et al.
patent: 6121906 (2000-09-01), Kim
patent: 61087416 (1986-05-01), None
patent: 08316831 (1996-11-01), None

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