Serial-to-parallel converter

Details Serial-to-parallel converter Serial-to-parallel converter

1987-10-06

1988-10-04

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

377 80, 377 70, 365219, G11C 700

Patent

active

047759909

ABSTRACT:
A serial-to-parallel converter has a number of memory cells connected in series for successively shifting input data in synchronism with a shift clock. The content of each memory cell is transferred by a latch circuit. The memory cells are provided with input terminals so that they can be set to "1" or "0" simultaneously before the entry of input data. This resetting, or presetting, reduces the number of reversals of the output polarity of the memory cells and hence the power consumed by the circuit can be diminished.

REFERENCES:
patent: 2951230 (1960-08-01), Cadden
patent: 3305738 (1967-02-01), Kintner
patent: 3743858 (1973-07-01), Woods
patent: 3972034 (1976-07-01), Derickson, III et al.
patent: 4063119 (1977-12-01), Odell et al.
patent: 4250406 (1981-02-01), Alaspa
patent: 4387294 (1983-06-01), Nakamura et al.
patent: 4396829 (1983-08-01), Sugihara et al.
patent: 4429300 (1984-01-01), Yamasawa et al.
patent: 4441198 (1984-04-01), Shibata et al.
patent: 4581740 (1986-04-01), Kinoshita
"Deserializer", p. 653, IBM Technical Disclosure Bulletin, vol. 14, No. 2, Jul. 1971.

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