Serial to parallel conversion with phase locked loop

Details Serial to parallel conversion with phase locked loop Serial to parallel conversion with phase locked loop

1996-10-01

1998-10-06

Hoff, Marc S.

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

375376, H03M 900

Patent

active

058183655

ABSTRACT:
A serial to parallel conversion circuit uses a dynamic shift register in a phase locked loop for an index to access a parallel holding register. The composite input signal includes serial data to be sampled and a synchronizing signal at an integer factor of the sampling serial data rate. The phase locked loop generates a control signal for sampling the serial data at a multiple of the synchronizing frequency by incorporating a delay between a variable frequency oscillator output and a phase comparator input. The delay element in one embodiment includes a shift register with a walking-one pattern that overflows to the phase comparator. The walking-one pattern is used to identify which position of the holding register should store the next sample of the input signal. The shift register is self-initialized by a logic combination of all shift register outputs. Power dissipation by the serial to parallel conversion circuit is minimal because only one 7-transistor shift register cell draws current at a time.

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