Serial to parallel conversion circuit

Details Serial to parallel conversion circuit Serial to parallel conversion circuit

1994-06-16

1996-10-01

Hoff, Marc S.

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

377 47, H03M 900

Patent

active

055614230

ABSTRACT:
The invention realizes a serial to parallel conversion circuit which operates at a high speed with low power dissipation. High speed serial data are input and re-timed with a high speed clock input by a first high speed flip-flop. Differential divide-by-eight clock signals are produced by dividing the high speed differential clock input by two using a second high speed flip-flop and are supplied to ninth through eleventh flip-flops, by which divide-by-eight shift clock signals and another series of divide-by-eight shift clocks leading the divide-by-two clocks by a half-period are produced. The output of the first high speed flip-flop is input to a shift register comprising first through fourth flip-flops, and is shifted with the positive phase divide-by-two clock signals. The output of the shift register is then re-timed with the other divide-by-eight shift clock signals described above by twelfth through fifteenth flip-flops. Similarly, the output of the first high speed flip-flop is shifted with the negative phase two-division clocks by fifth through eighth flip-flops and is re-timed with the divide-by-eight clocks by sixteenth through nineteenth flip-flops. The outputs of the twelfth through nineteenth flip-flops serve as outputs of the serial to parallel conversion circuit.

REFERENCES:
patent: 5155487 (1992-10-01), Tanaka et al.
patent: 5223833 (1993-06-01), Akata

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