Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-02-20
2003-07-01
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S189120, C365S221000
Reexamination Certificate
active
06587374
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a serial storage device having a memory cell array addressable in n-bit words.
BACKGROUND OF THE INVENTION
In reading data in a serial storage device such as a video memory, the data are retrieved simultaneously from a memory cell array in sequence in a multiplicity of bits (e.g. 8-bit and 16-bit words) to store them in registers so that the stored data may be serially output subsequently therefrom by shifting them in the registers. Also in writing data, they are written to designated memory cells of the array in words.
FIG. 1
shows a structure of a conventional serial storage device utilizing an array
1
of non-volatile memory cells known as electrically erasable programmable read only memory (EEPROM).
As shown in
FIG. 1
, the memory array
1
has a matrix of 32 rows and 4 columns of memory cells each forming an 8-bit word. Each of the memory cells is a non-volatile memory cell such as an EEPROM. A decoder
2
is provided to select a row out of the 32 rows of the matrix using word lines WL. A selector
3
is provided to select a column out of the 4 columns of the matrix using a column selection signal YA using bit lines BL(
0
-
31
). The address of a word is thus defined by the decoder
2
and the selector
3
. In this way the addressing of memory cells is performed in 8-bit words.
In the write operation, data lines DL
0
-DL
7
receives one word data, which are then written to addressed memory cells of the array. In the read operation, data retrieved from the addressed memory cells onto the data lines DL
0
-DL
7
are “read” by determining the potential levels (“0” or “1”) of the signals on the lines by the sense amplifiers
4
associated with the respective data lines. The read data (“0”s or “1”s) are stored in a shift register
5
. The data bits stored in the shift register
5
are then serially sent therefrom in synchronism with a clock (not shown) as the output data DO.
In this way, in a conventional serial storage device, read and write operations are both carried out in words. In particular, in the read/write operation to EEPROM, it is necessary to process data in words since a write to EEPROM takes a long time (as much as about 10 ms for example). Data reads are also performed in words, in harmony with the data write.
However, such word-wise processing of data read requires the same number of sense amplifiers and data lines as the number of the bits of each word. Consequently, the storage device needs a fairly large area for the required number of sense amplifiers and the data lines.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a serial storage device which is addressable in words by a reduced number of sense amplifiers and data lines than as required in conventional serial storage devices, to thereby reducing the dimensions and the peak currents of the storage device in operation.
In accordance with one aspect of the invention, there is provided a serial storage device, comprising:
at least one memory cell array addressable in multiple n-bit memory cells;
selection means for partitioning the addressed n-bit memory cells into k (≧2) groups each having n/k bits and for selecting the n/k-bit memory cell groups in sequence;
n/k sense amplifiers for determining the n/k bit data selected by said selection means and output from said addressed memory cells; and
a register for parallelly receiving the output of the sense amplifiers and for serially outputting them as readout data. The addressing of the memory cells of the array may be made by a row and a column selection signals.
Thus, the invention evaluates or determines the contents of each n/k-bit group of a selected n-bit (e.g. 8-bit or 16 bit) word. Accordingly, the sense amplifiers, and hence the data lines, required for the determination of the word are reduced in number by a factor of 1/k. This implies that the dimensions of the serial storage device and the peak currents thereof are reduce accordingly.
The selection means of the invention may be formed of
a first selector for selecting from the row of memory cells selected by said row selection signal, n-bit memory cells addressed by said column selection signal; and
a second selector for partitioning said n-bit memory cells into n/k-bit groups (k≧2) and for sequentially selecting said n/k-bit groups in sequence.
The selection means may be alternatively adapted to select from the row of memory cells selected by said row selection signal n-bit memory cells addressed by said column selection signal, further partition said n-bit memory cells into k groups of n/k bits and sequentially selecting said k groups by a group selection signal.
In this way n/k bit memory cells may be easily selected from an addressed n-bit memory cell group.
The n/k-bit data to be output next can be selected by the second selector and determined by the n/k sense amplifiers while the register is serially outputting the readout data.
Since the next n/k bit data are determined by the sense amplifiers while the current n/k bit data are being output from the register, n-bit readout data may be serially delivered from the register continuously and without any delay.
Each of the memory cells in the memory cell array of the invention is electrically writable and erasable non-volatile memory cells. The memory array is provided with one or more common array source ground lines for each group of n-bit memory cells. The n/k bit memory cells are dispersively distributed with respect to the array source ground lines in a manner as described below.
In this distributed arrangement of the memory cells, the rise of source potential of the memory cells during a read operation caused by read currents through impedances of the diffusion layers connecting each of the memory cells with the array source ground lines is reduced. As a result, the invention attains a uniform power distribution to the memory cells, high speed read operation, and reliable operation of the sense amplifiers.
The serial storage device of the invention may include a latch adapted to sequentially latch, via the second selector, externally supplied n/k-bit data on the locations of the latch selected by the second selector, and write the latched n-bit data to the addressed locations of the memory cell array via the first selector.
Thus, the invention allows temporary storage of n-bit data in the latch
14
as the data is input in n/k bits, and writing the whole n-bit data to the memory cell array at a time, thereby carrying out write operation without spending extra time if receiving data in n/k bits. Furthermore, the write can be done using reduced numbers of sense amplifiers and data lines.
The serial storage device of the invention may be provided with a page buffer of j×n bits for storing externally supplied n/k-bit sequential data in the j (j≧1) word locations of the page buffer selected by the selection means, and for writing the whole data (j words) at a time to memory locations of the memory cell array as addressed by the selection means.
The page buffer enables quick write to the memory cell array, since the page buffer can sequentially latch therein j words (j×n bits) while receiving data in n/k bits and write the whole data to the memory cell array at a time using reduced sense amplifiers and reduce data lines. It will be appreciated that the write can be done in a still shorter time.
REFERENCES:
patent: 5815444 (1998-09-01), Ohta
patent: 6034910 (2000-03-01), Iwase
patent: 6097640 (2000-08-01), Fei et al.
Katsuhara Noriaki
Tada Yoshihiro
Takagi Hiroki
Hogan & Hartson LLP
Mai Son
Rohm & Co., Ltd.
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