Serial rate conversion circuit with jitter tolerant payload

Details Serial rate conversion circuit with jitter tolerant payload Serial rate conversion circuit with jitter tolerant payload

1992-10-16

1995-06-13

Chin, Stephen

Pulse or digital communications

Miscellaneous

375371, H04L 2300, H04L 700

Patent

active

054250625

ABSTRACT:
A serial rate conversion circuit converts the serial rate of a stream of signals, for example, from a SONET overhead data link (ODL) rate of 6.48 Mb/s to and from a data communications channel (DCC) rate of 4.096 Mb/s. The circuit includes a low data flow memory and address select circuit for communicating the stream of serial formatted signals at a low data flowrate and a high data flow memory and address select circuit for communicating the stream of serial formatted signals at a high data flowrate. Clock rate conversion circuitry associates between the low data flow memory and address circuit and the high data flow memory and address select circuit to convert the high data flow serial formatted signals back and forth between the low data flowrate and the high data flowrate while maintaining said stream in a serial format. To provide jitter tolerance during the serial rate conversion process, the high data flowrate frame associates with the low data flowrate frame so that the low data flowrate frame elements are cushioned or buffered by leading and following high data flowrate frame elements.

REFERENCES:
patent: 4229815 (1980-10-01), Cummiskey
"Technical Terms" Second edition, Daniel N. Lapedes, McGraw-Hill, 1978.

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