Serial-parallel-serial charged coupled device memory and a metho

Details Serial-parallel-serial charged coupled device memory and a metho Serial-parallel-serial charged coupled device memory and a metho

1983-10-20

1985-01-08

Moffitt, James W.

Static information storage and retrieval

Addressing

Byte or page addressing

365183, G11C 1134

Patent

active

044930607

ABSTRACT:
An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and first storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage element of the output register. By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.

REFERENCES:
patent: 4165541 (1979-08-01), Varshney et al.
patent: 4199691 (1980-04-01), Angle
patent: 4211936 (1980-07-01), Kosonocky et al.
patent: 4288864 (1981-09-01), Harroun et al.
patent: 4306160 (1981-12-01), Hamilton
patent: 4382193 (1983-05-01), Grueter
IBM Technical Disclosure Bulletin-vol. 25, No. 11B, Apr. 1983, pp. 6172-6174.

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