Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
2000-02-22
2001-07-10
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S101000
Reexamination Certificate
active
06259387
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a serial-parallel converter circuit for converting serial data which have been inputted time-sequentially into parallel data, and more particularly to a serial-parallel converter circuit capable of relaxing a timing-restriction in high speed operation.
A conventional serial-parallel converter circuit is disclosed in Japanese laid-open patent publication No. 4-38017.
FIG. 1
is a diagram illustrative of the conventional serial-parallel converter circuit. The conventional serial-parallel converter circuit comprises a shift resistor
10
for generating latch timing, a flip-flop group
12
of flip-flop circuits
121
,
122
,
123
and
124
, a transit resistor
14
, and an output-stage resistor
16
. The shift resistor
10
receives a clock signal CLK and a signal LOAD, so that the conventional serial-parallel converter circuit converts the serial data DIN into parallel data D
01
, D
02
, D
03
and D
04
which have plural bits.
The shift resistor
10
for generating the latch timing is connected to an OR-gate
18
. The shift resistor
10
receives a clock signal CLK and a signal LOAD, so that the shift resistor
10
outputs four latch signals L
1
, L
2
, L
3
and L
4
in pulse form which are different in phase by one-cycle of the clock. The number of the outputted latch signals L
1
, L
2
, L
3
and L
4
corresponds to the number of the bits of the parallel data or four bits.
The flip-flop group
12
comprises the four flip-flip circuits
121
,
122
,
123
, and
124
which are connected to the shift resistor
10
, so that the first flip-flop
121
receives the first latch signal Li, the second flip-flop
122
receives the second latch signal L
2
, the third flip-flop
123
receives the third latch signal L
3
, and the fourth flip-flop
124
receives the fourth latch signal L
4
. Each of the four flip-flip circuits
121
,
122
,
123
, and
124
receives a time-sequential input of the serial data DIN, so that each of the four flip-flip circuits
121
,
122
,
123
, and
124
latches the serial data DIN on the basis of the latch signal L
1
, L
2
, L
3
or L
4
as the clock.
The transit resistor
14
is connected to the first and second flip-flops
121
and
122
for receiving output data DT
01
and DT
02
from the first and second flip-flops
121
and
122
respectively, so that the transit resistor
14
latches the output data DT
01
and DT
02
. The transit resistor
14
is also connected to the shift resistor
10
for receiving the third latch signal L
3
from the shift resistor
10
, so that the transit resistor
14
latches the output data DT
01
and DT
02
on the basis of the third latch signal L
3
as a clock.
The output stage resistor
16
is connected to the transit resistor
14
for receiving output data DT
11
and DT
12
from the transit resistor
14
. The output stage resistor
16
is connected to the third and fourth flip-flops
123
and
124
for receiving the third and fourth output data DT
13
and DT
14
from the third and fourth flip-flops
123
and
124
respectively. The output stage resistor
16
is also connected to the shift resistor
10
for receiving the second latch signal L
2
from the shift resistor
10
, so that the output stage resistor
16
performs to latch the output data DT
11
, DT
12
, DT
13
and DT
14
on the basis of the second latch signal L
2
as a clock signal, whereby the output stage resistor
16
outputs parallel data D
01
, D
02
, D
03
and D
04
.
FIG. 2
is a timing chart illustrative of waveforms of various signals of the conventional serial-parallel converter circuit of FIG.
1
. During when serial data signals DIN are inputted into the flip-flop group
12
in synchronizing with the external clock signal CLK, the first to fourth latch signals L
1
, L
2
, L
3
and L
4
are transmitted from the shift resistor
10
to the flip-flop group
12
as clocks, so that the first to fourth output signals DT
01
, DT
02
, DT
13
, and DT
14
are sequentially outputted from the first to fourth flip-flops
121
,
122
,
123
and
124
respectively.
Subsequently, the output signals DT
01
and DT
02
from the first and second flip flops
121
and
122
are transmitted to the transit resistor
14
and latched by the same on the basis of the third latch signal L
3
as a clock, so that the first and second output signals DT
11
and DT
12
are outputted from the transit resistor
14
.
The output signals DT
11
and DT
12
from the transit resistor
14
are transmitted to the output stage resistor
16
. Further, the output signals DT
13
and DT
14
from the third and fourth flip-flops
123
and
124
are transmitted to the output stage resistor
16
. The output signals DT
11
and DT
12
and the output signals DT
13
and DT
14
are latched by the output stage resistor
16
on the basis of the second latch signal L
2
from the shift resistor
10
, whereby parallel data D
01
, D
02
, D
03
, and D
04
are outputted from the output stage resistor
16
.
Only the shift resistor
10
is required to show the high speed operation. Other circuits such as the flip-flop group
12
are allowed to operate in the timing of 8-divided cycle of the input clock signals. The above conventional serial-parallel converter circuit is suitable for the high speed operations.
As can be understood from
FIG. 2
, the above conventional serial-parallel converter circuit has a disadvantage in that there is restricted a time until the second latch signal L
2
is inputted into the output stage resistor
16
after the output data DT
13
and DT
14
are outputted from the transit resistor
14
and the output data are outputted from the third and fourth flip-flops
123
and
124
. This time restriction means that a set-up time as a timing between input data and clock is restricted.
For example, only 2-divided cycle of the input clock CLK or a time period from t2 to t3 corresponds to the set-up time for the output stage resistor
16
. The increase in frequency of the clock signals CLK in order to realize or improve the high speed performance shortens one cycle time of the clock signal CLK whereby the set-up time is also shortened. This makes it difficult to ensure a sufficient set-up time.
In the above circumstances, it had been required to develop a novel serial-parallel converter circuit free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel serial-parallel converter circuit free from the above problems.
It is a further object of the present invention to provide a novel serial-parallel converter circuit capable of ensuring a sufficient set-up time even when a clock signal frequency is high.
The present invention provides a serial-parallel converter which comprises: a plurality of data extraction units for sequentially extracting different bit values of serial data, which are sequentially inputted, for individually holding the different bit values for a time period corresponding to the same number of cycles of a clock signal as the number of the data extraction units until the plurality of data extraction units extract next bit values of the serial data; a delay unit connected to the plurality of data extraction units for receiving the data signals from the plurality of data extraction units and delaying the data signals to generate delay signals which synchronize with each other; and a parallel register connected to the delay unit for receiving the delay signals from the delay unit for latching the delay signals to output the delay signals simultaneously as parallel data.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
REFERENCES:
patent: 5223833 (1993-06-01), Akata
patent: 5321400 (1994-06-01), Sasaki et al.
patent: 5426784 (1995-06-01), Kawata et al.
patent: 5805088 (1998-09-01), Butter et al.
patent: 5862367 (1999-01-01), Chiao-Yen
patent: 0 220 802 (1985-05-01), None
patent: 0 813 153 (1997-12-01), None
NEC Corporation
Nguyen John
Young Brian
Young & Thompson
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