Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
2000-05-31
2002-01-15
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S101000
Reexamination Certificate
active
06339387
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a serial/parallel converter that enables fast processing with low current consumption.
2. Related Arts
A serial/parallel converter is frequently employed in an integrated semiconductor circuit Such a serial/parallel converter is, for example, one by which a plurality of serially input address signals from a system are output in parallel internally. This converter is employed for a system having an extremely high transfer rate, such as 800 Mbps or 1.6 Gbps, and a plurality of address signals are transmitted at an extremely high transfer rate. It is, therefore, necessary for the internal serial/parallel converter to latch, in a short period of time, address signals which are input at high speed and to output them in parallel with the same phase.
FIG. 35
is a diagram illustrating a conventional serial/parallel converter.
FIG. 36
is a timing chart for the serial/parallel converter in FIG.
35
. In this example circuit, a clock CLK is amplified by a clock amplifier C
36
and an internal clock S
55
is generated. The internal clock S
55
is divided by 4 by a frequency divider C
45
, and a clock S
64
for final latching is generated. Input data DATA is amplified by a data amplifier C
37
, and is transferred to corresponding flip-flop circuits C
38
through C
44
at the leading edges or trailing edges of the internal clock S
55
. That is, the flip-clop circuits C
38
, C
39
, C
40
and C
41
latch the input data DATA at the leading edges of the internal clock S
55
, while the flip-flops C
42
, C
43
and C
44
latch the input data DATA at the trailing edges of the internal clock S
55
.
As is shown in
FIG. 36
, the data DATA is transmitted synchronously with the leading edges of the clock CLK (internal clock S
55
), and is synchronously latched by the flip-flops with the leading edges and the trailing edges of the internal clock S
55
. In this example circuit, at time T
1
, where data Dn, Dn+
1
, Dn+
2
and Dn+
3
are latched by the corresponding flip-flops C
38
, C
39
, C
40
and C
41
, these data are latched by the flip-flops C
46
, C
47
, C
48
and C
49
at the leading edge of a final latch clock S
64
. During a period equivalent to four times the cycle of the clock CLK, the flip-flops C
46
through C
49
latch the data and output in parallel a set of four data (S
65
~S
68
)to four output terminals S
65
through S
68
.
As is described above, the conventional serial/parallel converter converts four serial data sets into four parallel data sets in synchronization with the leading edge of the ¼ frequency divided clock S
64
.
The above serial/parallel converter requires eleven flip-flop circuits for 4-bit serial/parallel conversion. In addition, since the flip-flops C
38
through C
44
perform data latching four times and the flip-flops C
46
through C
49
perform data latching one time, a total of 32 operations by the flip-flops are required for one conversion process, and the current consumption is increased. According to this, for the conversion of 8-bit serial data, the number of required flip-flop circuits and the number of operations will be increased and the current consumption will be also increased.
Further, when the frequency of the input clock is increased, the operation speed of the flip-flop that performs synchronous latching with the input clock has to correspond to that speed. Thus, the circuit must be so designed that it can be operated at a high speed with a higher current consumption. Therefore, when a large number of flip-flops are operated for one serial/parallel conversion, the current consumption will be further increased. In addition, for faster processing, a serial/parallel converter is required that can cope with the input of data synchronized with the leading edge and the trailing edge of the input clock.
The serial input data is supplied in synchronous with a flag signal indicating the head of the serial data, therefore it is required that a fetching of the serial input data should be initiated using the flag signal as a trigger, and a parallel data output should be output at a certain timing signal. However, it is not easy to generate the timing signal for parallel data output after the last serial data has been fetched. Especially difficult, while taking into account an operating delay time for a flip-flop circuit for fetching the last serial data, is generating a timing signal for parallel data output at the shortest timing.
In addition, a circuit is required which generates a control clock for fetching serial data using an externally supplied flag signal as a trigger. Since this circuit has its own operating delay time, the input of serial data synchronized with a fast clock is affected accordingly. Therefore, a circuit is required which can fetch serial data without being affected by the timing of a flag signal.
SUMMARY OF THE INVENTION
It is, therefore, one object of the present invention to provide a circuit which requires a smaller number of flip-flops and which performs serial/parallel conversion by using a smaller number of latch operations.
It is another object of the present invention to provide a serial/parallel converter which can even latch serial data synchronously with a faster input clock, and which consumes only a small amount of current.
It is an additional object of the present invention to provide a serial/parallel converter which can provide an optimal relationship between the timings for the termination of a serial data fetch process and the output of parallel data.
It is a further object of the present invention to provide a serial/parallel converter which can synchronize the fetching of serial data with a clock without being affected by the timing of a flag signal indicating the head of serial data.
To achieve the above objects, according to one aspect of the present invention, a serial/parallel converter, outputting, with the same phase and in parallel, a plurality of data which is input serially in synchronization with an input clock, comprises:
a pulse generator for generating a plurality of latch clocks synchronized respectively with input timings of the plurality of data;
a plurality of holding flip-flops for latching in order the plurality of data in response to the plurality of latch clocks; and
a plurality of output latch flip-flops for, in response to the last latch clock synchronized with input of the last data of the plurality of data, latching, in parallel, the plurality of data held by the holding flip-flops and the last input data.
According to the present invention, the number of required flip-flops can be reduced, and each flip-flop need perform latching only once for a single serial/parallel conversion, so that the amount of current consumption is reduced.
Further, to achieve the above objects, according to the second aspect of the present invention, a serial/parallel converter, outputting, with the same phase and in parallel, a plurality of data which is input serially in synchronization with an input clock, comprises:
at least two input latch flip-flops for latching the plurality of input data in synchronization with the input clock;
a pulse generator for generating a plurality of latch clocks synchronized with timings at which the plurality of data are held by the input latch flip-flops;
a plurality of holding flip-flips for latching in order the plurality of data held by the input latch flip-flops in response to the plurality of latch clocks; and
a plurality of output latch flip-flops for, in response to the last latch clock synchronized with the latching of the last data of the plurality of data to the input latch flip-flops, latching, in parallel, the plurality of data held by the holding flip-flops and the last data held by the input latch flip-flops.
In the above circuit, when the input latch flip-flops have a first latching speed and the holding flip-flops have a second latching speed lower than the first latching speed, the serial data transferred at high speed can be latched, and the total amount
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Wamsley Patrick
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