Serial-parallel and parallel-serial converter

Coded data generation or conversion – Digital code to digital code converters – Serial to parallel

Utility Patent

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Details

C341S101000

Utility Patent

active

06169500

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a fast serial-parallel converter and parallel-serial converter and frequency dividers included therein.
BACKGROUND ART
There is described in European Patent Application EP 479 296 A1 a serial-parallel converter that comprises a shift register which includes four D-flip-flops, an output register that includes four D-flip-flops, and a frequency divider that includes two D-flip-flops and an inverter. The frequency divider is coupled as a shift register, with the Q-output on the second D-flip-flop that is fed-back to the D-input of the first D-flip-flop via the inverter. The shift register and the frequency divider are clocked by an incoming clock, whereas the output register is clocked by a frequency divided signal taken out from the Q-output of the second D-flip-flop.
Serial data signals are taken into the D-input of the first D-flip-flop of the shift register, taken out from the Q-outputs of the shift register every fourth clock cycle, and fed-out as parallel data signals on the Q-outputs of the output register.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a frequency divider comprised of circuits that have the function of AND-gates with clocked memory circuits.
Another object of the present invention is to provide a fast and inexpensive frequency divider for use in converters, for instance.
A third object of the present invention is to provide a frequency divider which in addition to a frequency divided signal is also capable of producing a pulse signal.
A fourth object of the present invention is to provide a serial-parallel converter that is fast, inexpensive and uses the least possible different types of circuit
A fifth object of the present invention is to provide a parallel-serial converter that is fast, inexpensive and uses the least possible number of different types of circuit.
A sixth object of the present invention is to provide a high-speed block in which serial-parallel and parallel-serial conversion can both take place.
One problem with earlier known serial-parallel and parallel-serial converters is the difficulty in producing fast converters in a simple and cost-effective manner.
The present invention solves this problem by virtue of a construction with which each output is coupled to few inputs, therewith reducing the delays in the circuits. In distinction, incoming data signals are delayed in relation to incoming clock signals (or vice versa), so as to clock the data signals in the middle of the data. This reduces the error risk.
In one embodiment of the frequency divider it is utilized that different inputs have different input capacitances, so as to enable the delays in the circuits to be reduced by giving the inputs other uses than normal. With the intention of reducing the cost of the construction, solely so-called scan flip-flops are used, i.e. D-flip-flops with multiplexed inputs, and inverters and buffers.
One advantage afforded by the present invention is that the construction enables the serial-parallel converters and parallel-serial converters to be made faster than was earlier the case.
Another advantage afforded by the invention is that the frequency divider can also be used in other connections than converters.


REFERENCES:
patent: 4429300 (1984-01-01), Yamasawa et al.
patent: 5163092 (1992-11-01), McNesby et al.
patent: 5367300 (1994-11-01), Fong et al.
patent: 5774079 (1998-06-01), Zirngibl
patent: 5926120 (1999-07-01), Swenson et al.
patent: 42 14 612 (1993-11-01), None
patent: 0 346 896 (1989-12-01), None
patent: 0 397 198 (1990-11-01), None
patent: 0 479 296 (1992-04-01), None
patent: WO96/05658 (1996-02-01), None

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