Serial memory address decoding scheme

Details Serial memory address decoding scheme Serial memory address decoding scheme

2006-05-30

2006-05-30

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230090, C365S233100, C365S236000, C365S239000, C365S240000

Reexamination Certificate

active

07054218

ABSTRACT:
A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for accessing the memory. A pulse generator supplies an appropriate number of pulses to the series of decoders in accordance with a difference in a stored previous address and a received current address.

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