Pulse or digital communications – Transceivers – Transmission interface between two stations or terminals
Reexamination Certificate
1998-02-02
2001-04-10
Pham, Chi H. (Department: 2631)
Pulse or digital communications
Transceivers
Transmission interface between two stations or terminals
C375S360000
Reexamination Certificate
active
06215817
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a serial interface circuit useful, for example, in communication with supervisory and control equipment in telecommunication systems, including digital transmission systems, digital switching systems, and the like.
In such systems, it is common for a single supervisory and control unit to supervise and control a plurality of other units, such as switching units or trunk line units. Each of the supervised and controlled units is conventionally coupled to the supervisory and control unit by a clock signal line, a data signal line, and a scan signal line, forming a three-wire interface. Data are sent and received serially on the data signal line in synchronization with the clock signal, during intervals designated by the scan signal. The clock and scan signals are supplied by the supervisory and control unit.
A problem with this three-wire interface is the number of wires. When the supervisory and control unit is coupled to many supervised and controlled units, the labor involved in connecting three times that many interface wires during equipment installation, and checking the connections during equipment maintenance, is considerable. In addition, the supervised and controlled units have much wiring of their own, and it may be difficult to find space for three interface wires in locations where the wires will not be affected by crosstalk, and will not cause crosstalk in other signal lines.
It would therefore be desirable to replace the three-wire interface with an interface having fewer wires, such as one of various standard two-wire interfaces. Changing over to one of these standard interfaces, however, would require major alterations in signaling formats and protocols, and corresponding modifications of the circuits that transmit, receive, and process the interface signals. Telecommunication system operators are understandably reluctant to make such far-reaching changes in equipment carrying high volumes of public telephone or data traffic.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a serial interface that is compatible with a three-wire interface, but requires fewer than three wires.
According to a first aspect of the invention, a serial interface circuit is coupled by a data signal line and a scan signal line to a partner interface circuit. On the scan signal line, the partner interface circuit transmits a scan signal indicating the beginning of a communication period. On the data signal line, the partner interface circuit transmits data, for at least part of the communication period, in synchronization with a first clock signal which is not transmitted.
In the serial interface circuit, a clock oscillator generates a second clock signal having N times the frequency of the first clock signal, where N is an integer greater than one. A clock frequency divider divides the frequency of the second clock signal by N, generating a divided clock signal, the phase of which is referenced to the scan signal. A data transceiver receives data on the data signal line in synchronization with the divided clock signal, and may also transmit data on the data signal line in synchronization with the divided clock signal.
According to a second aspect of the invention, the serial interface circuit is coupled by a data signal line and a clock signal line to the partner interface circuit. The partner interface circuit transmits data on the data signal line, in synchronization with a clock signal transmitted on the clock signal line. The data transmitted in each communication period start with a synchronization pattern.
In the serial interface circuit, a receiving shift register receives and stores data from the data signal line, in synchronization with the clock signal. A data comparator detects a timing when data stored in the receiving shift register match the synchronization pattern. A data transceiver recognizes this timing as the start of a communication period, and begins receiving data. The data transceiver may also transmit data.
According to a third aspect of the invention, the serial interface circuit is coupled only by a data signal line to the partner interface circuit. The partner interface circuit transmits data in synchronization with a non-transmitted first clock signal, in communication periods that begin with the transmission of a synchronization pattern.
In the serial interface circuit, a clock oscillator generates a second clock signal with N times the frequency of the first clock signal. A shift register with a length at least N times the length of the synchronization pattern receives and stores data from the data signal line, in synchronization with the second clock signal. A data comparator outputs a synchronization signal when the data stored in the shift register have a bit pattern matching the synchronization pattern, with each bit in the synchronization pattern repeated N times. A clock frequency divider divides the frequency of the second clock signal by N, generating a divided clock signal, the phase of which is referenced to the synchronization signal. A data transceiver receives data on the data signal line in synchronization with the divided clock signal, and may also transmit data on the data signal line in synchronization with the divided clock signal.
REFERENCES:
patent: 4477912 (1984-10-01), Russell
patent: 4527275 (1985-07-01), Russel
patent: 5430771 (1995-07-01), Fix et al.
Corrielus Jean B.
Frank Robert J.
OKI Electric Industry Co., Ltd.
Pham Chi H.
Sartori Michael A.
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