Serial input/output semiconductor memory

Details Serial input/output semiconductor memory Serial input/output semiconductor memory

1989-09-14

1991-05-21

Popek, Joseph A.

Static information storage and retrieval

Addressing

Combined random and sequential addressing

365221, 365240, G11C 700

Patent

active

050181106

ABSTRACT:
A semiconductor memory includes a random access memory (RAM) and a serial access memory (SAM). The RAM includes a memory cell array including memory cells. The SAM includes a data register including a plurality of bit cells which store bits of data read out from the memory cell array and assigned consecutive numbers, a first data bus line which is connected to odd numbered bit cells of the data register, a second data bus line which is connected to even numbered bit cells of the data register, a switching circuit for outputting serial data from the data register by alternately connecting to one of the first and second data bus lines, a first reset circuit for resetting the first data bus line when active, a second reset circuit for resetting the second data bus line when active, and a control circuit for selectively making the first and second reset circuits active so that a data transfer period of one of the first and second data bus lines starts prior to an end of a data transfer period of the other of the first and second data bus lines.

REFERENCES:
patent: 4322635 (1982-03-01), Redwine
patent: 4412313 (1983-10-01), Ackland et al.
patent: 4646272 (1987-02-01), Takasugi
patent: 4688197 (1987-08-01), Novak et al.
patent: 4740923 (1988-04-01), Kaneko et al.
patent: 4825411 (1989-04-01), Hamano

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