Serial frame processing system in which validation and transfer

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3642705, 364271, 3642386, 364239, 364DIG1, G06F 1300

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active

051330784

ABSTRACT:
An asynchronous high-speed data interface for coupling a serial channel to a parallel control unit. A first state machine, running synchronously with the channel transmitter clock, controls the filling of a pair of dual-port input buffers in alternating fashion with frame contents bytes from incoming serial frames that have been deserialized and decoded. A second state machine, running synchronously with a second clock that is asynchronous with the channel transmitter clock, controls the transfer of the frame contents bytes from the selected input buffer to one of a pair of output buffers en route to the control unit. Upon detecting the receipt of the third incoming frame contents byte, the first state machine sets a start latch, causing the second state machine to begin transferring data from the selected input buffer to the selected output buffer while the input buffer is still being filled. Means are provided for disregarding the frame contents bytes that have been transferred to the selected output buffer if the frame is ultimately aborted.

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