Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-10-10
2002-04-30
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185230
Reexamination Certificate
active
06381173
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a serial-flash, EPROM, EEPROM and flash EEPROM nonvolatile memory in AMG (Alternate Metal Ground) configuration.
BACKGROUND OF THE INVENTION
As is known, floating gate EEPROM memory cells are programmed (written and/or erased) by Fowler-Nordheim effect, by injecting or extracting charges, through a thin tunnel oxide region, by applying appropriate voltages between the terminals of the cells. In particular, it is necessary to supply high voltages to control terminals of cells to be programmed, which are selected by enable transistors.
For greater clarity, reference is made to
FIG. 1
, which shows an example of a known architecture of an EEPROM memory array
1
, belonging to a memory device
15
. The memory array
1
comprises a plurality of cells
2
, arranged on rows and columns, and each comprises a sense transistor
3
and a select transistor
4
. The cells
2
are connected to one another in groups, to form memory bytes, comprising each for example eight cells
2
.
FIG. 1
shows two cells
2
belonging to a single byte.
In detail, the control gate terminals of the sense transistors
3
that belong to a single byte are connected by a gate line
5
to a source terminal of a respective byte enable transistor
6
. In addition, the sense transistors
3
have source terminals connected to a common source line
8
, which can be alternatively grounded or left floating by a selector
13
, and drain terminals, each of which is connected to a source terminal of a respective select transistor
4
.
The drain terminals of the select transistors
4
are each connected to a respective bit line
10
.
FIG. 1
shows two bit lines
10
that belong to the same byte, and are designated respectively as BLO and BL
7
. The select transistors
4
of cells
2
which belong to a single array row also have gate terminals which are connected to a word line
11
.
The byte enable transistor
6
, which comprises an N-channel MOS transistor, has a gate terminal connected to the word line
11
, and a drain terminal connected to a control gate line
12
.
The known devices have some disadvantages. In particular, during erasing of the cells
2
, the control gate line
12
, via the byte enable transistor
6
, must feed the control gate terminals of the cells
2
to be erased with high voltages, for example 14 V. However, a voltage drop exists between the drain and source terminals of the byte enable transistor
6
and thus the control gate line
12
must be set to a voltage higher than that required for erasing.
In addition, the byte enable transistor
6
has a high threshold voltage, since it is N-channel, and, as shown in
FIG. 2
, it is formed directly in a P-type substrate region
20
of the memory device
15
. In detail, the byte enable transistor
6
comprises a source region
21
and a drain region
22
, both of N
+
type, embedded in the substrate region
20
, and defining a channel region
23
. In addition, the substrate region
20
defines a bulk region. Normally, the substrate region
20
is at a voltage close to 0 V, and thus, during erasing, high voltages are established between the source region
21
and the bulk of the byte enable transistor
6
.
It is known that the threshold voltage of MOS transistors increases as the bulk-source voltage increases (so-called body effect). Consequently, because of this high voltage, there is a considerable increase in the threshold voltage of the byte enable transistor
6
, and the latter can transfer to the source terminal a reduced portion of the voltage that is present at the drain terminal. Therefore, it is necessary to generate and feed the drain terminal of the byte enable transistor
6
with a voltage that is considerably higher than the voltage that must be applied to the control gate terminals of the cells
2
. This requires pumping circuits of an appropriate size, as well as involving higher energy consumption. In addition, it is necessary to provide specific processing phases to produce high voltage components, with high breakdown voltage.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a non-volatile memory that is free from the disadvantages described, and in particular reduces the body effect on the byte enable transistors, includes a byte enable transistor having an input terminal, connected to a control gate line and receives an input voltage, an output terminal, connected to at least one memory cell and supplying an output voltage, a control terminal connected to a word line, and a bulk region housing conductive regions connected to the input and output terminals. The byte enable transistor is a P-channel MOS transistor, the bulk region whereof is biased to a bulk voltage that is not lower than the input voltage.
REFERENCES:
patent: 6128219 (2000-10-01), Pio et al.
patent: 6128220 (2000-10-01), Banyai
Iannucci Robert
Jorgenson Lisa K.
Nguyen Tan T.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
LandOfFree
Serial-flash, EPROM, EEPROM and flash EEPROM nonvolatile... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Serial-flash, EPROM, EEPROM and flash EEPROM nonvolatile..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Serial-flash, EPROM, EEPROM and flash EEPROM nonvolatile... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2862865