Serial FFT processing unit

Details Serial FFT processing unit Serial FFT processing unit

1976-06-18

1977-11-15

Malzahn, David H.

Boots, shoes, and leggings

G06F 1534

Patent

active

040587150

ABSTRACT:
An FFT processing unit of simplified construction comprises one or more arithmetic stages serially connected. Each stage has a plurality of recursive arithmetic paths each consisting of a delay element, a simplified multiplier for multiplying by .+-.1 and .+-.j where j = .sqroot.-1, and an adder. The adder is supplied with a serial input digital data series and the output is provided to the delay element and multiplier connected in series. A switch successively selects the output signals obtained from the plurality of recursive arithmetic paths. A second multiplier multiplies the signals selected by the switch by predetermined coefficients.

REFERENCES:
patent: 3588460 (1971-06-01), Smith
patent: 3686490 (1972-08-01), Goldstone
patent: 3899667 (1975-08-01), Simone

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