Serial data transfer device

Details Serial data transfer device Serial data transfer device

1999-04-26

2001-11-27

Lee, Michael (Department: 2614)

Television

Image signal processing circuitry specific to television

With details of static storage device

C348S663000, C348S718000

Reexamination Certificate

active

06323916

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a serial data transfer device for serially transferring data in synchronism with clocks, and more particularly to a serial data transfer device for transferring the data at the transfer timings made coincident when the same command is simultaneously issued to a plurality of circuits to be controlled.
2. Description of the Related Art
Generally, a television receiver or home video tape recorder (VTR) incorporates a plurality of ICs. In some cases, these ICs are controlled by a single controller (microcomputer). The control system includes a serial system and a parallel system. However, in many cases, the serial system which requires a less number of lines is used. The serial system creates a start signal, slave address signal, a transfer data, stop signal, etc. in combination of logic values of “H” and “L” of the data and clock and uses a repetition signal including these plurality of signals to constitute one cycle. In this case, the transfer data carry several kinds of information.
FIGS. 2A and 2B
show data and clocks in the serial data transfer device in such a serial system, respectively. Timing t
1
denotes a start point and timing t
2
denotes a stop point. Between these timings, necessary transfer data exist.
The start point indicates the timing when the data shifts from “H” to “L” while the clock is “H”. On the other hand, the stop point indicates the timing when the data shifts from “L” to “H” while the clock is “H”. The data is captured by reading the value of the data on the falling edge of the clock (e.g. t
3
).
Upon completion of the single data transfer, the stop signal is generated to inform the completion of the data transfer. A next start signal arrives and a next transfer data comes.
Such a serial transfer system takes a longer time where it is required that a command is simultaneously transferred to a plurality of ICs.
For example, a home video tape recorder requires for a plurality of ICs (e.g. main YC signal processing IC, head amplifier IC, and OSD IC) to be changed into a reproduction mode or a recording mode. In this case, transfer of the information for mode change in a serial manner cannot operate the plurality of ICs at the same timings.
At present, upon completion of the mode change in all the ICs, the mode is changed formally.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a serial data transfer device capable of controlling the transfer timings of serial data to be coincident at a high speed and with no image disorder.
In order to attain the above object, in accordance with first aspect of the present invention, there is provided a serial data transfer device for serially transferring data comprising: an input terminal to which a serial data is inputted; a first temporary memory for temporarily storing the serial data supplied from the input terminal; a first memory for storing the data supplied from the first temporary memory; a second temporary memory for temporarily storing the serial data supplied from the input terminal; a second memory for storing the data supplied from the second temporary memory; a first transfer state detecting circuit for generating a first control signal indicative of that the serial data supplied from the input terminal is being transferred; a second transfer state detecting circuit for generating a second control signal indicative of that the serial data supplied from the input terminal is being transferred; a control circuit for deciding that the first and the second control signal have not arrived in response to the arrival of a transfer command signal, thereby transferring the data from the first temporary memory to the first memory and transferring the data from the second temporary memory to the second memory, whereby in response to the transfer command signal, the data are simultaneously transferred to the first memory and the second memory.
The second aspect of the device is a device according to the first aspect, wherein the first transfer state detecting circuit generates a first transfer completion signal indicative of that the serial data has been transferred to the first memory; the second transfer state detecting circuit generates a second transfer completion signal indicative of that the serial data has been transferred to the second memory; and in response to the arrival of the transfer command signal, the control circuit decides that the first and second control signals do not still come and the first and second transfer completion signals have come, thereby transferring the data from the first temporary memory to the first memory and transferring the data from the second temporary memory to the second memory.
The third aspect of the device is a device according to the second aspect, wherein the control circuit comprises: a system control circuit for generating a control pulse and a detection pulse delayed from the control pulse in timing in accordance with a change of the state of a transfer pulse indicative of the transfer command signal; a latch decision circuit for deciding whether or not the first and second control signal have not arrived while the control pulse is generated by the system control circuit; and a switch for passing or stopping the detection pulse in accordance with a decision output signal from the latch decision circuit.
The fourth aspect of the device is a device according to any one of the first to the third aspect, wherein said transfer command signal is a vertical synchronizing signal of a video signal.
The fifth aspect of the device is a device according to any one of the first to the third aspect, wherein said transfer command signal is an RF switch pulse signal.
The sixth aspect of the device is a device according to any one of the first to the third aspect, wherein said transfer command signal is a C-ROT pulse signal.
The seventh aspect of the device is a device according to any one of the first to the third aspect, wherein said transfer command signal is an HA switch pulse.
The eighth aspect of the device is a device according to any one of the first to the third aspect, wherein said transfer command signal is an RF switch pulse signal and a vertical synchronizing signal.
The ninth aspect of the device is a device according to any one of the first to the third aspect, wherein said transfer command signal is a horizontal synchronizing signal located in a period which does not appear on a screen.
The tenth aspect of the present invention is a serial data transfer device for serially transferring data which comprises:
an input terminal
1
to which a serial data is inputted;
a first temporary memory
2
for temporarily storing the serial data supplied from the input terminall;
a first memory
3
for storing the data supplied from the first temporary memory;
a second temporary memory
4
for temporarily storing the serial data supplied from the input terminal;
a second memory
5
for storing the data supplied from the second temporary memory;
a first transfer state detecting circuit
6
for generating a first control signal A
1
indicative of that the serial data supplied from the input terminal is being transferred;
a second transfer state detecting circuit
7
for generating a second control signal A
2
indicative of that the serial data supplied from the input terminal is being transferred;
a system control circuit
21
for generating a control pulse and a detection pulse delayed from the control pulse in timing in accordance with a change of the state of a transfer pulse indicative of the transfer command signal;
a latch decision circuit
23
for deciding whether or not said first and second control signal have not arrived while said control pulse is generated by the system control circuit; and
a switch
22
(
10
,
11
)for passing or stopping the detection pulse in accordance with a decision output signal from the latch decision circuit, thereby transferring the data from the first temporary memory to the first memory and transferring the data from the second

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