Serial data transfer circuits for delayed output

Details Serial data transfer circuits for delayed output Serial data transfer circuits for delayed output

1985-06-03

1987-06-09

Miller, Stanley D.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

377 67, 377 70, 377107, 328105, G11C 1900

Patent

active

046726470

ABSTRACT:
A power-saving serial data transfer circuit for outputting an inputted digital data signal through a plurality of serially connected shift register cells comprises n (=m.times.k) cells in k groups each containing m serially connected cells. A digital data signal is applied commonly to the first-stage cells of the groups and inputted in a time-wise segmented sequence to the cells by shift pulses with different phases. The inputted data signal is shifted through the cells within the same groups and is inputted to the last-stage cells of the groups. The inputted data signal is also outputted through a multiplexer connected to the last stage cells.

REFERENCES:
patent: 3972034 (1976-07-01), Derickson, III et al.
patent: 4263583 (1981-04-01), Wyckoff
patent: 4353057 (1982-10-01), Bernet et al.

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