Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2008-04-09
2011-12-20
Flores, Leon (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S324000, C375S326000, C375S327000, C375S340000, C375S354000, C375S371000, C375S373000, C375S375000, C375S376000, C455S260000, C455S502000, C455S516000, C327S141000, C327S147000, C327S156000, C714S707000
Reexamination Certificate
active
08081723
ABSTRACT:
Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.
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Y. Tomita et al., “A 10-Gb/s Receiver with Series Equalizer and On-Chip ISI Monitor in 0.11-micron CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, No. 4, Apr. 2005, pp. 986-993.
Ding Weiqi
Shumarayev Sergey
Tran Thungoc M.
Wong Wilson
Altera Corporation
Flores Leon
Ropes & Gray LLP
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