Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Patent
1990-11-14
1992-08-04
Pellinen, A. D.
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
377 69, H03M 900
Patent
active
051362929
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a serial data receiving circuit for data processing apparatus such as a digital signal processor (hereinafter referred to as DSP), a microcomputer or the like.
BACKGROUND TECHNOLOGY
Prior art in this field is disclosed in "OKI SEMICONDUCTOR INTEGRATED CIRCUIT DATA BOOK '88" (published on November of 1987) or "STANDARD LOGIC IC" p. 859.
An arrangement of the prior art will be described hereafter.
FIG. 2 is a block diagram showing an arrangement of a prior art data processing apparatus for the DSP, the microcomputer or the like.
The data processing apparatus 5 comprises a serial interface circuit 1 for transmitting a signal to and receiving the signal from an external device and an internal signal processing circuit 4 in which the serial interface circuit 1 is composed of a serial data receiving circuit 2 and a serial data transmitting circuit 3. According to this data processing apparatus, when serial data Di are input to the serial data receiving circuit 2 the serial data Di are converted to parallel data Da by the serial data receiving circuit 2 and supplied to the internal signal processing circuit 4. The parallel data Da are subjected to a given processing in the internal signal processing circuit 4 and supplied to the serial data transmitting circuit 3 as a parallel data Db. Upon reception of the parallel data Db, the serial data transmitting circuit 3 converts the parallel data Db to serial data Do which are supplied to the external device.
FIG. 3 is a block diagram showing an arrangement of the serial data receiving circuit 2 in FIG. 2.
The serial data receiving circuit 2 comprises, for example, a shift register, for providing eight bits parallel outputs, which is composed of a 2 input AND gate 10 and D-type flip-flops (hereinafter referred to as D-FF) 11 to 18. The D-FFs 11 to 18 each has a reset terminal R for receiving a clear signal CLR, a clock terminal CK for receiving a clock signal CLK and an output terminal Q. Each is connected to one another in that each output terminal Q is connected in series to parallel data output terminals PO0 to PO7. The clock signal CLK and a clock inhibit signal CLKINH are respectively connected to inputs of the AND gate 10. An output of the AND gate 10 is connected to each clock terminal CK of the D-FFs 11 to 18.
FIG. 4 is a timing chart for when the serial data receiving circuit 2 in FIG. 3 receives five bits of data.
In the serial data receiving circuit 2, the input serial data Di (=D0, D1, ..., D4) are successively transferred to the D-FFs 11 to 18 under the control of the clock signal CLK. The parallel data Da (=D0, D1, ..., D4) are provided from the output terminals PO0 to P07 which are connected to each output terminal Q of the D-FFs 11 to 18.
That is, when the clear signal CLR is allowed to be a logical "1" and the D-FFs 11 to 18 are reset, a logical "0" is provided from the output terminals PO0 to P)7. When the clear signal CLR is allowed to be a logical "0" and the clock inhibit signal CLKINH is allowed to be the logical "1", the input signal data D4 to D0 are successively transferred to the D-FFs 11 to 18 at the leading edge of the clock signal CLK by way of the AND gate 10. Upon completion of the input of the signal data D4 of the 5th bit, the clock inhibit signal CLKINH is allowed to be the logical "0" so that the input of the five bits of data D4 to D0 is completed. At this time, the parallel data Da, composed of "000D4 D3 D2 D1 D0", are provided from the output terminals PO7 to PO0.
However, the serial data receiving circuit having the arrangement set forth above has the following problems.
(a) When the prior art serial data receiving circuit 2 is provided in the data processing apparatus such as the DSP or the microcomputer or the like, as illustrated in FIG. 2, the parallel data Da, provided by the serial data receiving circuit 2, are processed by the internal signal processing circuit 4. In the DSP or the like, there are many data formats adopting twos complement representation.
However, in case
REFERENCES:
patent: 5016011 (1991-05-01), Hartley et al.
Manzo Edward D.
OKI Electric Industry Co., Ltd.
Pellinen A. D.
Young B. K.
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