Serial data processing circuit

Pulse or digital communications – Synchronizers

Reexamination Certificate

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Details

C375S355000, C375S326000, C375S327000, C375S376000

Reexamination Certificate

active

07903773

ABSTRACT:
A serial data processing circuit that realizes the same performance as that of the pipeline processing with low power consumption. First to fourth latch units receive, in parallel, data sets supplied to a logic circuit. These latch units sequentially latch the data sets sequentially supplied to the logic circuit and output N data sets in parallel. A Selector sequentially selects the data sets supplied from these latch units and supplies the selected data sets to the logical circuit. For example, when the first latch unit latches data (a), the selector selects the data (a) and supplies it to the logic circuit. When the second latch unit latches data (b), the selector selects the data (b) and supplies it to the logic circuit. The logic circuit processes N serial data sets during each cycle.

REFERENCES:
patent: 5459843 (1995-10-01), Davis et al.
patent: 7254205 (2007-08-01), Gabara et al.
patent: 7340021 (2008-03-01), Churchill et al.
patent: 7440532 (2008-10-01), Chang
patent: 2006/0004992 (2006-01-01), Fujisawa et al.
patent: 2008/0165902 (2008-07-01), Moriwaki
patent: 5-224929 (1993-09-01), None
patent: 2006-18539 (2006-01-01), None

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