Serial data encoder

Excavating

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G06F 1100

Patent

active

052854558

ABSTRACT:
Sequential encoding of Reed-Solomon codes using a discrete time delay line, a single adder, and a single multiplier provides efficient encoding of Reed-Solomon codes with or without interleaving. The encoder utilizes a clock whose rate is r times the symbol rate where r is the redundancy of the code. The finite field operations are performed in a sequential manner requiring only one finite field multiplier and one finite field adder. All memory elements are consolidated into a discrete time delay line which can be implemented with a random access memory. The encoder can be easily reconfigured for changes in generator polynomial of the code, the amount of redundancy, and interleaving depth.

REFERENCES:
patent: 4680764 (1987-07-01), Suzuki et al.
patent: 4777635 (1988-10-01), Glover

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