Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2000-10-02
2004-06-29
Vo, Don N. (Department: 2631)
Pulse or digital communications
Equalizers
Automatic
C375S257000, C375S348000, C375S350000
Reexamination Certificate
active
06757327
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to serial data communication receivers for data capture and clock recovery and, more particularly, to a receiver and method for terminating a serial data signal.
Serial communication receivers are used in integrated circuits, such as application specific integrated circuits (ASICs), for clock synchronization and for recovery of serial data streams from transmission channels. Clock signals and data are recovered by detecting transitions in the serial data stream and the valid data between those transitions. The time and voltage ranges over which the data is valid within each cycle in the stream is known as the data “eye”. In order to minimize bit errors in the recovered data, the serial data stream is preferably sampled near the center of this eye. However, the limited-bandwidth nature of a transmission channel results in distortion and closure of the data eye in both the time and voltage domains.
One current method of limiting distortion and closure of the data eye at the receiver is to provide equalization of the incoming data signal through a high-pass filter, or equalizer, which is located either on-board or on-chip. The equalizer boosts the voltage sensitivity of the receiver at those frequencies at which attenuation of the incoming data signal due to the frequency response of the transmit media rolls off. The net effect is an extension in the flat region of the frequency response of the combination of the transmitter, the transmit media and the receiver.
In addition, one or typically both ends of the transmission line are resistively terminated to a reference voltage such as a power supply terminal or a ground terminal. The total effective termination resistance is matched to the impedance of the transmission line to minimize reflection and distortion of the transmitted data signals. However, the impedance of the transmission line can vary with each application. Therefore, the fixed termination resistance in the receiver may not be optimal for a particular application.
A serial data communication receiver is desired that is capable of evaluating the performance of a complete transceiver system, which includes the transmit media, and adjusting the termination resistance in the receiver to compensate for this performance and essentially open the eye of the incoming data stream.
SUMMARY OF THE INVENTION
One aspect of the -present invention is directed to a method of adaptively terminating a received serial data signal. The method includes terminating the received serial data signal with a variable termination resistance. The received serial data signal is equalized with an equalizer to produce an equalized serial data signal. The equalized serial data signal is then de-serialized. The termination resistance is varied over a range of termination resistance values while equalizing and de-serializing. A data eye size of the equalized serial data signal is measured for each of the termination resistance values, and the termination resistance is set to one of the termination resistance values based on the measured data eye sizes.
Another aspect of the present invention relates to a serial data communication receiver, which includes a serial data input and a termination resistance that is coupled to the serial data input and is variable over a range of termination resistance values. An equalizer circuit is coupled to the serial data input and has an equalized serial data output. First and second capture latch circuits are coupled to the equalized serial data output, within a phase-locked loop, and have first and second recovered data outputs, respectively. A termination resistance control circuit measures a data eye size of the equalized serial data output based on the first and second recovered data outputs over the range of termination resistance values and sets the termination resistance to one of the termination resistance values based on the measured data eye sizes.
Yet another aspect of the present invention relates to a serial data communication receiver, which includes a serial data input and a termination resistance that is coupled to the serial data input and is variable over a range of termination resistance values. First and second equalizers are coupled to the serial data input and have first and second equalized outputs. The first equalizer applies a voltage offset to the first equalized output, which is variable based on a voltage offset control input. First and second capture latch circuits are coupled to the first and second equalized outputs, respectively, in a phase-locked loop and have first and second recovered data outputs, respectively. The first capture latch circuit has a variable sample time relative to the second capture latch circuit based on a delay control input. A comparator is coupled to the first and second recovered data outputs through first and second comparator inputs, respectively, and has an error output. A termination resistance control circuit is coupled in a feedback loop between the error output and the termination resistance control input to control the voltage offset and delay control inputs and adjust the termination resistance based a resulting error on the error output.
REFERENCES:
patent: 5633899 (1997-05-01), Fielder et al.
patent: 5757865 (1998-05-01), Kaku et al.
patent: 6320834 (2001-11-01), Tsuchinaga
patent: 6643787 (2003-11-01), Zerbe et al.
“Rate-Independent” CDR Chip Locks In At Up To 2.7 Gbits/s,Electronic Design, (Mar. 20, 2000) http://www.elecdesign.com/magazine/2000/mar2000/coverstory/cov1.shtml?ads=communication.
LSI Logic Corporation
Vo Don N.
Westman Champlin & Kelly
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