Pulse or digital communications – Pulse width modulation
Reexamination Certificate
1998-08-26
2001-08-14
Chin, Stephen (Department: 2634)
Pulse or digital communications
Pulse width modulation
C375S219000, C370S276000
Reexamination Certificate
active
06275526
ABSTRACT:
BACKGROUND OF THE INVENTION
Contemporary very large scale integration (VLSI) technology commonly includes one or more communication circuits incorporated with standard logic functions in a single integrated circuit (IC) chip or functional module. Between ICs, data can be serially transmitted via a communication line using one of several conventional serial transmission techniques including: synchronous input/output (I/O) communication, UART (Universal Asynchronous Receiver/Transmitter), and I
2
C communication.
In synchronous I/O communication, the transmitting and receiving functions are synchronized using an auxiliary signal, for example a clock. Each function includes a controller for effecting serial transmission. At least two communication lines are required (clock and data lines), along with an auxiliary control line for enabling/disabling the communication circuit.
UART technology is designed to operate in both transmit and receive directions. Eight data lines operate as a parallel interface for internal logic, and a fully-structured serial interface is provided for a serial communication line. The UART further includes a control block for enabling serial transmission.
The UART transmission technique suffers from relatively limited signal transmission speed. Furthermore, when the control block is incorporated in an IC module, it occupies a relatively large portion of the IC circuit area, and further generates electromagnetic interference (EMI) noise resulting from rapid toggling of data and clock signals. During serial communication, a parity bit is commonly inserted into a serial data frame as a data integrity check, and a complementary data signal may be transmitted with the original data to effect transmission verification at the receiver. Such verification techniques generally require a complicated circuit configuration in the communication circuit and signal transmission system.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for serial data transmission between communication circuits of IC functional modules in a manner which overcomes the limitations of the prior art.
It is an object of the present invention to provide a communication circuit adapted for reducing EMI radiation when data is transmitted serially over a communication line.
It is another object of the invention to provide a communication circuit of relatively simple construction and relatively small chip occupation area.
It is a further object of the invention to provide a communication circuit which has a simple data verification protocol.
In accordance with the above objects, the present invention is directed to a serial communication circuit including an encoder for producing a first pulse signal having a programmable pulse duration which is representative of a data value. A decoder restores the data value from the first pulse signal received from the encoder. A data line is coupled between an output terminal of the encoder and a data input terminal of the decoder. A controller programs the pulse duration at the encoder based on the data value, and restores the data value at the decoder based on the first pulse signal duration.
According to a preferred embodiment of the invention, the duration of the pulse signal comprises an initial pulse having a predetermined time duration and a data pulse comprising a summation of unit time intervals, each unit time representing a data value.
The initial pulse duration corresponds to a representation of the start of the data pulse. The time interval of the initial pulse may be shorter than, equal to, or longer than the unit time interval of the data pulse.
A complementary pulse signal may also be generated at the encoder which is the complement of the first pulse signal. The complementary pulse signal is transmitted simultaneously with the first pulse signal on a complementary data line. Both signals are received at the decoder and restored to their data values. If the data values are equal, an acknowledge signal is transmitted to the encoder to indicate that the data has been properly received. If they are not equal, the data is resent.
According to this invention, since the serial data transmitted via the data line has a single pulse format (i.e., the data values are encoded in time duration, rather than voltage), EMI is effectively prevented. Also, electromagnetic radiation is considerably reduced as compared with radiation occurring during conventional synchronous communication using clock signals or during the UART communication. Thus, communications circuitries or modules adopting this data transmission technique can be relatively free of noise problems.
Further, as the transmitter and receiver of the invention can be formed of relatively small constitutional elements, the communication circuitry may occupy a relatively small portion of the chip surface area when it is integrated into an IC module.
In addition, according to this invention, a simple data verification and error detection for the transmitted data is possible since the first pulse data signal and its complementary pulse signal are received simultaneously by the receiver and an acknowledge signal is sent back to the transmitter when the two restored data pulses have the same value. Thus, erroneous transmission of data resulting from outside noise can be avoided during serial communication.
REFERENCES:
patent: 3922486 (1975-11-01), DeJean
patent: 4178549 (1979-12-01), Ledenbach et al.
patent: 5185765 (1993-02-01), Walker
patent: 5216667 (1993-06-01), Chu et al.
patent: 5469285 (1995-11-01), Gut
patent: 5905716 (1999-05-01), Vidales
Al-Beshrawi Tony
Chin Stephen
Mills & Onello LLP
Samsung Electronics Ltd.
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