Serial data clock recovery circuit using dual oscillator circuit

Details Serial data clock recovery circuit using dual oscillator circuit Serial data clock recovery circuit using dual oscillator circuit

1994-02-07

1995-05-23

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

331 25, 331 48, 331 55, 331 56, 331DIG3, 375363, 375376, H03L 7099, H04L 708

Patent

active

054184967

ABSTRACT:
A serial data clock receiver circuit (11) is provided that synchronizes a clock signal to data. The serial data clock receiver circuit (11) comprises a control circuit (21), a dual oscillator circuit (19), and a phase locked loop circuit (22). The control circuit (21) arms the dual oscillator circuit (19) for being enabled during an idle period. The phase locked loop circuit (22) provides a reference voltage for the dual oscillator circuit (19). The dual oscillator circuit (19) is responsive to both the data and control circuit (19) for providing a clock signal.

REFERENCES:
patent: 4523158 (1985-06-01), Megeid
patent: 4633488 (1986-12-01), Shaw
patent: 5237290 (1993-08-01), Banu et al.
Banu et al., "TA 6.4: a 660 Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission", Jan. 1993 IEEE International Solid State Circuits Conference.
Banu et al., "Clock Recovery Circuits with Instantaneous Locking", Nov. 5, 1992, vol. 28, No. 23, Electronics Letters, pp. 2127-2130.

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