Serial correlator architecture

Details Serial correlator architecture Serial correlator architecture

2011-05-10

2011-05-10

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07941472

ABSTRACT:
An apparatus for correlating multibit first and second words includes a multiplexer for selecting one bit at a time of the second word, and applying the bit to a multiplier which receives the first word, for generating a product by inverting or noninverting the first word. The product is applied to an adder and is added to a delayed parallel signal to produce a sum signal. The sum signal is delayed in an amount related to the number of bits in the first word to produce the delayed parallel signal. A plurality of such apparatuses are cascaded, with the bits of the second word applied in subsets to the apparatuses, and the partial correlations applied as input words to the next apparatus in the cascade.

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