Serial communication system

Details Serial communication system Serial communication system

2008-03-14

2010-12-28

Kumar, Pankaj (Department: 2467)

Electrical computers and digital processing systems: multicomput

Master/slave computer controlling

Reexamination Certificate

active

07860939

ABSTRACT:
A serial communication system includes a master processor and a slave processor. A CS signal for requesting a serial communication is output from the master processor, and an OK_INV signal for responding to the CS signal is output from the slave processor. When a CS signal is an active state, the master processor executes a serial communications of a preset number of bits every time that a level of the OK_INV signal is reversed. The slave processor inverts a level of an OK_INV signal in response to the CS signal shifting to the active state. The slave processor changes the level of the OK_INV signal every time that a serial communication of a preset number of bits is completed.

REFERENCES:
patent: 5737630 (1998-04-01), Kobayashi
patent: 2004/0158333 (2004-08-01), Ha et al.
patent: 2007/0061496 (2007-03-01), Nishino
patent: 5-46549 (1993-02-01), None
Translation of JP 05-046549 provided in the IDS.

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