Serial clock generating circuit

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

328141, H04L 700

Patent

active

052205851

ABSTRACT:
A serial clock generating circuit is configured to frequency-divide an input clock having a frequency which is a number times a serial data transfer rate, so as to generate a serial clock in phase with a received serial data. The serial clock generating circuit comprises an edge detection circuit for detecting a level change of a received serial data so as to generate a level change signal. Three registers stores different set values, and a latch latches one of the different set values. A decrementer decrements the value of the latch in response to each input clock, and a memory circuit holds an arbitrary value for defining a phase deviation discrimination area. A comparison circuit compares the value stored in the memory circuit with the value of the latch at each one input clock, and generates a coincidence signal when a coincidence is obtained. An area detection circuit discriminates a level change position on the basis of the level change signal and the coincidence signal and selects one of the registers to be set to the latch. A flipflop is coupled to the decrementer for generating a serial clock on the basis of the result of the counting of the decrementer.

REFERENCES:
patent: 4896337 (1990-01-01), Bushy, Jr.
patent: 4931986 (1990-06-01), Daniel et al.
patent: 5056120 (1991-10-01), Taniguchi et al.

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