Multiplex communications – Diagnostic testing
Reexamination Certificate
1999-03-10
2003-05-06
Vincent, David (Department: 2732)
Multiplex communications
Diagnostic testing
C710S100000
Reexamination Certificate
active
06560200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to serial bus experimental apparatus and more particularly to serial bus experimental apparatus that allows the capturing of a series of massive packets transferred over a serial bus and their processing such as display, and/or that allows the transmission of a packet including an error to a node instrument to be tested.
2. Related Background Art
In recent years, the serial bus named IEEE 1394 (hereinafter, called as “High Performance Serial Bus”) has been in practical use. This bus has allowed a personal computer to be connected with printers, digital cameras, external hard disks and the like in a daisy chain or in a tree structure, so that high speed communication between any node instruments has been allowed. The high performance serial bus features that a large number of node instruments can be connected with a small cable and further a massive amount of data, such as dynamic image data, can be easily transferred through the small cable.
As shown in
FIG. 6
, a high performance serial bus
1
comprises serial bus cables
1
1
-
1
n−1
connecting a plurality of node instruments
2
1
-
2
n
in serial. Each node instrument
2
i
includes physical layer circuit
4
i
and link layer circuit
5
i
which perform protocol control for serial communication in hardware level according to instructions of the high order controller
3
i
. The physical layer circuit
4
i
is connected to serial bus cables
1
i−1
,
1
i
. When the physical layer circuit
4
i
receives a transmission signal transmitted over the serial bus cable
1
i−1
(or
1
i
) from other node instrument, it outputs the same transmission signal to the serial bus cable
1
i
(or
1
i−1
). At the same time, the physical layer circuit
4
i
also converts the transmission signal to reception data, and outputs the reception data to the link layer circuit
5
i
. Further, when the physical layer circuit
4
i
receives transmission data from the link layer circuit
5
i
, it converts the transmission data to a transmission signal and outputs the transmission signal through the serial bus cables
1
i−1
and
1
i
.
The link layer circuit
5
i
produces a transmission packet destined for other node instrument according to instructions of the high order controller
3
i
and outputs a transmission data stream composing the transmission packet to the physical layer circuit
4
i
. Specifically, in the case of an isochronous packet for which transfer of 125 micro-second-cycle is guaranteed, upon receipt of header information including data lengths, channel numbers and synchronization codes and data from the controller
3
i
, the link layer circuit
5
i
produces an isochronous packet (see FIG.
7
), conforming to a predetermined format, composed of an integral multiple of four bytes while adding a header CRC and data CRC, obtained by calculation, for error detection/correction and the like. Then, it outputs to the physical layer circuit
4
i
the transmission data row from the first bit of it in groups of 2 bits (a transfer speed of 100 Mbps), in groups of 4 bits (a transfer speed of 200 Mbps) or in group of 8 bits (a transfer speed of 400 Mbps). In the case of an asynchronous packet that is transferred asynchronously, there are some differences such that a destination ID and source ID are added to the header information as a substitute for the channel number and the like.
Further, when the link layer circuit
5
i
receives a reception data stream from the physical layer circuit
4
i
, it takes out a reception packet for its own node to capture from the data rows and outputs the packet to the controller
3
i
. The link layer circuit
5
i
and the physical layer circuit
4
i
receive and transmit control signals through three control lines CTL
0
, CTL
1
and LReq, and also receives and transmits transmission data or reception data by handshaking using two lines D
0
and D
1
of eight data lines D
0
-D
7
(in the case of a transfer speed of 100 Mbps), four lines D
0
-D
3
(in the case of a transfer speed of 200 Mbps) and eight lines D
0
-D
7
(above 400 Mbps). In addition, the physical layer circuit
4
i
performs bus arbitration at the time of transmission and also outputs a clock SCLK synchronized with the control signals and data which are transmitted to the link layer circuit
5
i
or received from it.
Serial bus experimental apparatus for carrying out performance tests on various node instruments connected to the high performance serial bus has been developed. The serial bus test apparatus, as shown by a reference numeral
2
n
in
FIG. 6
, is also connected to the bus as one of node instruments in the same way as the other node instruments. It also includes a controller
3
n
for a bus test comprising a microprocessor for example, a link layer circuit
5
n
, a physical layer circuit
4
n
, a memory
10
, a display
11
and a operational panel
12
. For example, when it is desired to test on a node instrument
2
1
which performs isochronous transfer on a channel number
1
, the following have been stored in the memory
10
in advance. That is, various test data to be used in a test on the node instrument
2
1
, the channel number on which the node instrument
2
1
performs isochronous transfer, the ID of the node instrument
2
1
, the ID of the serial bus experimental apparatus and the like.
When the activation of the node instrument
2
1
is directed through the operational panel
12
, the controller
3
n
outputs the following to the link layer circuit
5
n
, referring to the memory
10
. That is, header information including a transfer speed (here, assumed to be 100 Mbps), the destination ID which is the ID of the node instrument
2
1
, the source ID which is the ID of the serial bus experimental apparatus and the data length of the asynchronous packet, and data including the activation instruction. The link layer circuit
5
n
produces an asynchronous packet (
FIG. 5
) conforming to a predetermined format adding a header CRC, data CRC and the like and, at the same time, notices transmission request and the transfer speed to the physical layer circuit
4
n
through the control line LReq. Then, when the physical layer circuit
4
n
wins the arbitration of access to the high performance serial bus and provides transmission permission for the link layer circuit
5
n
through the control lines CTL
0
, CTL
1
, the link layer circuit
5
n
outputs to the physical layer circuit
4
n
the transmission data in groups of two bits from the first of the asynchronous packet using the data line D
0
and D
1
in synchronization with the clock SCLK. At this moment, the link layer circuit
5
n
outputs over the control lines CTL
0
, CTL
1
a control signal to indicate that transmission data is being outputted.
The physical layer circuit
4
n
receives the transmission data, converts the data to an electrical transmission signal conforming to the standard and outputs the signal to the high performance serial bus.
When the link layer circuit
5
n
has finished outputting a packet of transmission data and has no packet to transmit, it outputs a control signal to indicate the completion of transmission over the control lines CTL
0
, CTL
1
. Receiving the control signal, the physical layer circuit
4
n
shifts to another processing.
When the node instrument
2
1
receives the asynchronous packet of the transmission signal transmitted from the serial bus experimental apparatus
2
n
and transmits back an isochronous packet of a transmission signal at a transfer speed of 100 Mbps in a fixed cycle, the physical layer circuits
4
2
-
4
n
in all the other node instruments
2
2
-
2
n
receive the transmission signal and convert it to reception data and output it to the link layer circuits
5
2
-
5
n
. At this moment, the physical layer circuits
4
2
-
4
n
output over the control lines CTL
0
, CTL
1
control signals to indicate that the reception data is being outputted.
When the control signals to indicate that the reception data is being outpu
Kabushiki Kaisha Kenwood
Robinson Eric J.
Robinson Intellectual Property Law Office
Vincent David
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