Multiplex communications – Pathfinding or routing – Through a circuit switch
Patent
1996-03-11
1998-10-06
Marcelo, Melvin
Multiplex communications
Pathfinding or routing
Through a circuit switch
370391, 370536, 341 61, H04L 1256
Patent
active
058188347
DESCRIPTION:
BRIEF SUMMARY
This invention relates to a time division switching matrix capable of effecting rate conversion.
Many digital telephone systems are based on the transport of time multiplexed, serialized PCM (pulse coded modulation) encoded voice bytes. PCM is an 8 bit encoding scheme for digitizing an analog voice signal, sampled at 8 khz. Different telephone networks employ different degrees of multiplexing between the bytes flowing serially at a rate of 8 bits per 125 microseconds (the period of 8 khz.). Popular schemes include time division multiplexing of 32 voice channels (for a net data rate of 2.048 megabits per second), 64 voice channels (for 4.096 megabits per second) or 128 voice channels (for 8.192 megabits per second) onto single PCM highways.
Most if not all digital networks require switching between logical channels in the interconnected PCM highways. Hitherto this has been performed with rate conversion circuitry.
FR-A-2,376,572 discloses a typical time division switching matrix including a a circuit capable of multiplexing incoming serial multiplex streams onto a supermultiplex parallel stream. This employs serial-to-parallel and parallel-to-serial converters associated with each input or output respectively. This patent does not, however, suggest any means for effecting rate conversion within the switch.
According to the present invention there is provided a time division switching matrix capable of effecting rate conversion comprising a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of serial outputs for connection to respective serial output links, each capable of carrying time division multiplexed PCM channels, and a serial-to-parallel converter associated with each input for converting a serial input stream to parallel format. The serial-to-parallel converters are shift registers that are reconfigurable to produce the same net parallel throughput regardless of the bit rate of the associated input link, said shift registers are staggered in length to delay the time at which the input data are ready to be parallel loaded, and for different data rates unique input shift register clocks are provided to properly shift the input data at the desired data rate.
The invention allows for rate conversion in the switching matrix, for example, between PCM highways of 2.048 megabits per second, and 4.096 megabits per second, or 2.048 megabits per second and 8.192 megabits per second. It also allows for conversion from 8.192 megabits per second to 2.048 megabits per second, or 4.096 megabits per second and 2.048 megabits per second. With rate conversion, networks with differing serial backplanes can be interconnected.
In the preferred embodiment, the switching core of the device consists of a ram based time switch that switches 256.times.256 channel locations. During each 125 microsecond frame 256 bytes of incoming PCM data are written in sequence into a data ram. During the frame, 256 reads of the same memory fetch PCM data bytes, which are shifted out onto serial output links. The time at which the fetch occurs determines the output link and channel number that the PCM data is to be routed to.
The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:
FIG. 1 is a diagram showing the memory address timing for a switching matrix in accordance with the invention;
FIG. 2 is a diagram showing the inputs shift registers for the 2 Mb/s mode;
FIG. 3 shows the input data stream redirects for the 4 Mb/s mode;
FIG. 4 shows the input data stream redirects for 8 Mb/s mode;
FIG. 5 shows the 2 Mb/s configuration;
FIG. 6 shows the output data stream redirects for the 4 Mb/s mode;
FIG. 7 shows the 8 Mb/s timing;
FIG. 8 shows the output data stream redirects for the 8 Mb/s mode; and
FIG. 9 is a block diagram of a switching matrix in accordance with the invention.
The switching matrix shown in FIG. 9 comprises input Mux 1, 2 each containing reconfigurable sh
REFERENCES:
patent: 5337181 (1994-08-01), Rogers
patent: 5343467 (1994-08-01), Wohr
patent: 5359605 (1994-10-01), Urbansky et al.
patent: 5471466 (1995-11-01), Cooperman
Lehmann Jim
Skierszkan Simon
Lee Chiho Andrew
Marcelo Melvin
Mitel Corporation
LandOfFree
Serial bit rate converter embedded in a switching matrix does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Serial bit rate converter embedded in a switching matrix, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Serial bit rate converter embedded in a switching matrix will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-86948