Serial bit pattern recognizer system

Details Serial bit pattern recognizer system Serial bit pattern recognizer system

1994-09-21

1995-10-17

Tse, Young

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

370106, H04L 700

Patent

active

054597544

ABSTRACT:
A recognizer system having a transmitter for transmitting and a receiver receiving a serial stream of bits that includes data bits and a predetermined bit pattern. The recognizer system recognizes the predetermined bit pattern. A bit of the serial stream of bits is directly inputted from the receiver into a memory due to a clock pulse on the memory. The memory is programmed with decision tree statements of a decision tree. A initial state value, stored in a latch, is also inputted, from the latch, into the memory, due to the clock pulse on the memory. A next state value is immediately outputted from the memory. The outputted next state value replaces the initial state value stored in the latch, due to a delayed clock pulse on the latch. The next state is available to the memory. A signal bit is also outputted from the memory to a user device for the digital data. The system continues until a predetermined bit pattern produces a final state of a decision tree out of the memory. At that time a signal bit, of value one, indicates that the predetermined bit pattern has been received from the receiver and allows the user device to receive data bits from the receiver.

REFERENCES:
patent: 4575864 (1986-03-01), Rice, Jr. et al.
patent: 4727558 (1988-02-01), Hall
patent: 4730346 (1988-03-01), Jiang
patent: 4799218 (1989-01-01), Sakagami et al.
patent: 4847877 (1989-07-01), Besseyre

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