Serial address generator for burst memory

Details Serial address generator for burst memory Serial address generator for burst memory

1994-06-24

1995-09-19

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365221, 365236, 365239, 36523006, 36523008, G11C 800

Patent

active

054522617

ABSTRACT:
A serial address generator for a sequential (burst mode) random access memory generates a sequence of internally generated addresses for fast cycling. The start address is externally provided. Then, as the clock signals arrive, the subsequent addresses are generated in sequence by the address sequencer. The address sequencer is preset to the second address in the sequence following the start address. Simultaneously, the start address is connected by an external address enable switch to an output terminal of the address generator, bypassing the address sequencer. When the first clock signal arrives at the address sequencer, the address sequencer output is sampled by closing an internal address enable switch and opening the external address enable switch. Thus the internally generated addresses are provided immediately following the start address. The address sequencer thereby generates each address one clock cycle ahead of that in the prior art, and the output address is provided one half clock cycle ahead of that in the prior art.

REFERENCES:
patent: 5097447 (1992-03-01), Ogawa
patent: 5146431 (1992-09-01), Eby
patent: 5260905 (1993-11-01), Mori

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