Serial access memory with column address counter and pointers

Details Serial access memory with column address counter and pointers Serial access memory with column address counter and pointers

1993-06-18

1995-03-14

Popek, Joseph A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365221, 365233, 365236, 365240, G11C 800

Patent

active

053982096

ABSTRACT:
A serial access memory has multiple memory blocks, each with a row-and-column array of memory cells for storing data. Data access is synchronized with a clock signal. A column address counter counts the clock signal to generate a column address. A block selector decodes upper bits of the column address to generate a series of block select signals, which are distributed to the memory blocks. In each memory block a shift register receives and shifts one block select signal to generate a series of column select signals.

REFERENCES:
patent: 4890262 (1989-12-01), Hashimoto et al.
patent: 4954994 (1990-09-01), Hashimoto
IEEE Journal Of Solid-State Circuits., vol. 26, No. 4, Apr. 1991, N. Y. US, pp. 502-506, Kuriyama et al. "An 8 NS 4 Mb Serial Access Memory, " p. 502, left column, line 26-p. 504, right column, line 19; figures 1-9.
1990 Symposium On VLSI Circuits, Jun. 1990, Honolulu USA, pp. 51-52, Kuriyama et al. "A 4 Mbit CMOS SPRAM With 8 NS Serial Access Time," the whole document.

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