Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent
1988-05-06
1990-02-20
Hecker, Stuart N.
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
365 78, 36518912, 377 73, G11C 1300, G11C 700
Patent
active
049032429
ABSTRACT:
A serial access memory circuit provided with an improved serial addressing circuit which can be fabricated with a reduced number of elements, is disclosed. The memory circuit comprises a memory array of N columns to be serially accessed, and a serial selection circuit including a shift register of N/K stages, a control circuit generating K output signals and a gate circuit receiving output signals of N/K stages of the shift register and K output signals of the control circuit and generating N output signals.
REFERENCES:
patent: 3665496 (1972-05-01), Donjon
patent: 3906195 (1975-09-01), Maejimra
patent: 4396829 (1983-08-01), Sugihava et al.
patent: 4641278 (1987-02-01), Saito
Hamaguchi Kunihiko
Ohara Yasuhide
Garcia Alfonso
Hecker Stuart N.
NEC Corporation
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