SERDES cooperates with the boundary scan test technique

Details SERDES cooperates with the boundary scan test technique SERDES cooperates with the boundary scan test technique

2002-10-08

2003-11-25

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C341S055000, C341S058000, C324S765010, C714S729000

Reexamination Certificate

active

06653957

ABSTRACT:

BACKGROUND OF THE INVENTION
A SERDES (an acronym standing for SERializer/DESerializer) is a component in a digital communications path that converts data from a multi-bit parallel channel into equivalent data that is then applied to a higher speed serial channel. Typically, the communications path is bi-directional, and to accommodate that a SERDES also converts data from the serial channel into equivalent data that is then applied to the parallel channel. Multi-bit parallel channels (as found in parallel bus architectures) often present performance difficulties when operated at high speeds over long distances. For example, there may be skew between the bits. A serial channel is often easier to operate, even at much higher speeds. A common use of SERDES circuits then, is to use them in pairs, one SERDES at each end of a “long” communications path that is parallel at each end, but serial in-between.
So, for example, a high speed interconnecting serial channel might operate at 2.5 GHz and be a differentially driven pair of transmission lines, or a fiber optic link, while the two parallel ports might be eight bits wide with a word rate of 250 MHZ. Viewed from afar, the SERDES is part of a (transparent) SERDES to SERDES connection that forms a (possibly long) eight bit parallel path clocked at 250 MHZ. (It will be noted that the information, or overall bit rate, in the interconnecting serial channel is higher than that for the parallel data being transported. Some of that extra capacity is used to facilitate serial channel “housekeeping” and will be of considerable interest in due course.) A typical application for such a pair of SERDES circuits is as transmitting and receiving mechanisms for high speed data paths between individual ICs (Integrated Circuits) located on the same printed circuit board, or perhaps located on different printed circuit boards within the same chassis and interconnected through a backplane. (There are, of course, other applications for SERDES circuits, but these are the ones of our immediate interest.) In such an arrangement a pair of SERDES circuits forms an essentially transparent mechanism that transports eight-bit words from one location (an IC or other environment) to another, as if accomplished by a bus, but without certain practical difficulties (e.g. bit-to-bit skew) that beset a bus operating at high frequencies.
For various reasons the high speed serial data (one bit wide) is sent as a differential pair. These reasons include speed of detection at the receiving end (twice the dv/dt is experienced by the differential receiver), common mode rejection by the receiver of noise induced in both sides of the signal, and noise generation avoidance through zero net change in currents flowing through ground and the power supply. What is more, each signal of the differential pair is often AC coupled. This allows SERDES of different manufacture or incompatible semiconductor families to cooperate. Typically, 4.7 uF capacitors are disposed on the PC board and are in series with the differentially driven transmission lines that couple the serial ports of the SERDES.
We have already indicated that the serial and parallel paths do not have the same bit rates: in the example set out above, eight times 250 M is not 2.5 G; there is a ten-to-one difference, instead of an eight-to-one difference. The difference in bit rates is accounted for by the use of a mapping that uniquely associates each of the possible two hundred and fifty-six eight-bit parallel bit patterns (it will be convenient to refer to these as “characters”—even if those bit patterns do not represent familiar alpha-numeric or typographical symbols) with a different serial pattern of ten bits, of which there are one thousand twenty-four. The mapping is an industry standard informally-called 8b10b, and the “surplus” seven hundred sixty-eight serial characters are used in various ways, among which is the definition of an entire class of control characters used for supervisory purposes in managing the operation of the serial channel. It will be noted that the mapping mechanism needs to be bi-directional, since a receiving SERDES needs to convert the ten-bit serial characters back into eight-bit parallel characters. At the block diagram level this mapping mechanism turns into an 8b10b encoder and a companion 10b8b decoder.
An important aspect of the 8b10b mapping is that it allocates to each pair of eight-bit parallel characters a pair of ten-bit serial patterns that, over the pair, has the same number of ones and zeros. Such balance is needed to keep the AC coupling in the high speed serial path from accumulating a charge (blocking) and subsequently attenuating the amplitude of the transmitted signal. Otherwise, there would exist sequences of eight bit data that would produce corresponding ten-bit sequences that were unbalanced, which if they are long enough, would charge the coupling capacitors completely, resulting in a serial channel malfunction.
Unfortunately, there are only two hundred fifty-two ten-bit characters that have five ones and five zeros, which means that a simple 8b10b scheme would have four eight-bit parallel characters that are associated with unbalanced serial characters. Long input sequences involving those particular parallel characters would be untenable, so the actual 8b10b scheme is “context sensitive” and alters the mapping, as needed, on alternate characters such that serial side is always balanced over at most twenty bits (corresponding to two input characters). This involves what is called a “disparity bit” and is a known mechanism. A related issue is the fact that no clock signal is explicitly sent from the transmitting SERDES to the receiving SERDES. Instead, the receiving SERDES performs clock recovery. While AC coupling requires balance, clock recovery benefits from regularly distributed transitions in the data, with the implication that some mappings from eight bits to ten bits are less desirable than others.
Operating in cooperation with the basic 8b10b encoding and 10b8b decoding is the coding and decoding of ten-bit framing characters that are periodically inserted in the serial traffic as part of an established SERDES protocol. This mechanism (packets separated by framing characters), in conjunction with initial training sequences and the practice of clock recovery, allow the receiving SERDES to “sync up” on the transmitting SERDES; both a frequency locked-loop and a phase-locked loop are involved. The tasks of generating and of recognizing such control characters are facilitated by defining the often used serial channel control characters (of which the “comma” K28.5 is one member of that family of characters) as some consecutive number of ones followed by some consecutive number of zeros, including the one's complement of those patterns. The patterns selected for this duty are five consecutive ones followed immediately by two consecutive zeros, and five consecutive zeros followed immediately by two consecutive ones. It turns out that this can be accomplished by assigning such meanings to otherwise unused “surplus” codes in the 8b10b scheme.
Now let us consider the issue of testability for large and complex printed circuit board assemblies having many ICs, such as the router cards and line cards found in industrial strength internet routers. It will be appreciated that some manufacturer's versions of those include pairs of SERDES, as described above.
A venerable prior art method of testing installed ICs involves a “bed of nails” that makes electrical contact between a test apparatus and useful locations upon a DUT (Device Under Test), which in this case is a printed circuit board assembly. Further connections are made to the lands of the edge connector(s) and any cables attached to the board. The test apparatus applies power, stimulus, and makes measurements. However, trends occurring over the last few decades have limited the applicability of such testing. These include high numbers of tiny traces, traces on interior layers of multi-layer boards, and high

Affiliated with

Also associated with

Rating

SERDES cooperates with the boundary scan test technique does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SERDES cooperates with the boundary scan test technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SERDES cooperates with the boundary scan test technique will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3169621