Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1997-11-17
2000-07-04
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
709 3, G06F 1516
Patent
active
060853034
ABSTRACT:
Improved method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka synchronization mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can be used to alert all processor entities (PEs) in a partition when all of the PEs in that partition have reached a designated barrier point in their individual program code, or when any one of the PEs in that partition has reached a designated eureka point in its individual program code, or when either the barrier or eureka requirements have been satisfied, which ever comes first. Multiple overlapping synchronization partitions are available simultaneously through the use of a plurality of parallel synchronization contexts. The present synchronization mechanism may be implemented on either a dedicated barrier network, or superimposed as a virtual barrier/eureka network operating on a physical data-communications network which is also used for data interchange, operating system functions, and other purposes. The present barrier/eureka mechanism also supports zero to N processor entities at each router node ("leaves" on the barrier tree), and provides a barrier sequence counter for each barrier context in order to resolve potential race conflicts that might otherwise arise.
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Passint Randal S.
Scott Steven L.
Thorson Greg
Coleman Eric
Cray Research Inc.
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