Sequentially built integrated circuit package

Details Sequentially built integrated circuit package Sequentially built integrated circuit package

1998-05-08

2000-08-22

Potter, Roy

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257706, 257712, 257723, H01L 2312

Patent

active

06107683&

ABSTRACT:
An enhanced ball grid array substrate package and method for manufacturing the same, where the substrate package includes a metal core having a first surface and a second surface opposite the first surface. The metal core further includes at least one cavity in which at least one integrated circuit is positioned. A dielectric layer is secured to the first surface of the metal core and includes at least one die cavity formed therein. Thereafter, a conductive seed layer is chemically deposited to exposed portions of the dielectric layer and the first surface of the metal core. Adjacent to the conductive seed layer, a circuit is electrolytically and selectively formed within a first circuit pattern.

REFERENCES:
patent: 5191511 (1993-03-01), Sawaya
patent: 5343360 (1994-08-01), Sanwo
patent: 5409865 (1995-04-01), Karnezos
patent: 5468994 (1995-11-01), Pendse
patent: 5557502 (1996-09-01), Banerjee et al.
patent: 5583378 (1996-12-01), Marrs et al.
patent: 5599747 (1997-02-01), Bhatt et al.
patent: 5650593 (1997-07-01), McMillan et al.
patent: 5661086 (1997-08-01), Nakashima et al.

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