Boots – shoes – and leggings
Patent
1980-01-08
1983-03-15
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1300
Patent
active
043769721
ABSTRACT:
A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tri-state operated address register circuits and timing circuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.
REFERENCES:
patent: 3440615 (1969-04-01), Carter
patent: 3812473 (1974-05-01), Tucker
patent: 4000485 (1976-12-01), Barlow et al.
Johnson Robert B.
Moore Dana W.
Nibby, Jr. Chester M.
Driscoll Faith F.
Honeywell Information Systems Inc.
Prasinos Nicholas
Zache Raulfe B.
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