Sequential timing circuitry for a semiconductor memory

Details Sequential timing circuitry for a semiconductor memory Sequential timing circuitry for a semiconductor memory

1976-01-14

1978-05-02

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307238, 307279, 307DIG1, 307DIG3, 307DIG4, 307DIG5, H03K 515, G11C 700, G11C 800, G11C 1140

Patent

active

040877043

ABSTRACT:
A semiconductor memory employs a variety of circuit elements which are used to manipulate the digital information stored within the rows and columns of the memory array. The circuit elements must be manipulated in an ordered sequence with proper relative timing to permit decoding of various addresses and other circuit commands and enabling of various ones of the circuit elements. The plurality of timing signals are generated within the memory by a corresponding plurality of timing generators. Accurate timing and sequencing is obtained by utilizing the output of one timing generator to trigger or initiate the generation of a signal in another generator followed by either proper conditioning upon an input signal, such as an address, or by a predetermined delay designed into the timing generator itself.

REFERENCES:
patent: 3778784 (1973-12-01), Karp et al.
patent: 3795898 (1974-03-01), Mehta et al.
patent: 3922647 (1975-11-01), Broeker, Jr.

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