Sequential successive approximation analog-to-digital converter

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307221D, 340347M, 357 24, H03K 1308

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043261922

ABSTRACT:
A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.

REFERENCES:
patent: 3100298 (1963-08-01), Fluhr
patent: 3156913 (1964-11-01), Crocker et al.
patent: 3701148 (1972-10-01), Frei
patent: 3930255 (1975-12-01), Means
patent: 4072938 (1978-02-01), Buchanan
patent: 4072939 (1978-02-01), Heller et al.
patent: 4107670 (1978-08-01), Hornak
patent: 4126852 (1978-11-01), Baertsch
The Engineering Staff of Analog Devices, Inc., Analog-Digital Conversion Handbook, 6/1972, pp. II-46 to II-48.

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