Sequential pulse deposition

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material

Reexamination Certificate

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C438S650000, C438S686000

Reexamination Certificate

active

06613656

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to deposition techniques and, more particularly, to deposition techniques for forming thin films on wafers or substrates.
BACKGROUND OF THE INVENTION
Integrated circuits (IC) are often fabricated with one or more semiconductor devices, which may include diodes, capacitors, and different varieties of transistors. These devices are generally fabricated by creating thin films of various materials, e.g. metals, semiconductors or insulators, upon a substrate or semiconductor wafer. The terms wafer and substrate used in the following description include any semiconductor-based structure having an exposed surface with which to form an integrated circuit or semiconductor device, and may include one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. Wafer and substrate are used interchangeably to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereon. The physical characteristics and tightly controlled placement of films on a substrate will define the performance of the semiconductor device and its surrounding circuitry.
Semiconductor fabrication continues to advance, requiring finer dimensional tolerances and control. Modem integrated circuit design has advanced to the point where line width may be 0.25 microns or less. As a result, repeatability and uniformity of processes and their results is becoming increasingly important.
One important process for depositing thin films on semiconductor wafers is chemical vapor deposition or CVD. CVD is used to form a thin film of a desired material from a reaction of vapor-phase chemicals containing the chemical constituents of the material.
CVD processes operate by confining one or more semiconductor wafers in a reaction chamber. The chamber is filled with one or more gases that surround the wafer. The gases for the deposition of metal and metal alloys includes a metal precursor and a reactant gas, e.g. an oxidizer or hydrogen gas, to be introduced into the chamber at the same time. Energy is supplied within the chamber and particularly to the reactant gases near the wafer surface. A typical energy is heat applied to the substrate. The energy activates the reactant gas chemistry to deposit a film from the gas onto the heated substrate. Such chemical vapor deposition of a solid onto a surface involves a heterogeneous surface reaction of the gaseous species that adsorb onto the surface. The rate of film growth and the quality of the film depend on the process conditions. Unfortunately, the metal precursor and the reactant gas also react during the gas phase. Such a gas phase reaction produces contaminants and/or involve a significant quantity of precursor so that an insufficient amount is available for deposition of the substrate. As a result, the gas phase reaction becomes dominant and the thin film coverage is poor.
Deposition of a film begins with nucleation as the atoms or molecules of the desired material begin to condense on the substrate and agglomerate to form nuclei. Growth of these nuclei will fill in the gaps between individual nuclei to develop a continuous surface or film. The gas phase reaction can also prevent the formation of a sufficient number of nuclei and/or the growth of the nuclei to fill the gaps therebetween due to insufficient reactions between the metal precursor and oxidizer at the surface of the wafer. For example, CVD techniques for depositing metal, e.g. platinum or platinum alloys, may result in non-uniform nucleation due to gas phase reaction of the metal gas and the oxidizer. Non-uniform nucleation can result in gaps and pinholes between g rains and short some of the circuitry. Uniform nucleation is desirable to create a uniform film so that the electrical and mechanical properties of the film, and hence wafer and resulting circuitry, are predictable, accurate and reproducible.
Generally, it is desired to have thin films deposited on the wafer to save space. Yet reducing the thickness of films can result in pinholes and in less mechanical strength. One area of particular concern is step coverage. Due to the rapidly changing geography at these step interfaces, thinner films face a larger risk that the film will be too thin in some areas to achieve the desired performance characteristics. Thus, nominally thicker films are sometimes unavoidable to provide adequate step coverage where the deposition process encounters high aspect ratios for steps in the substrate topology. CVD techniques for depositing metal or metal alloys on substrates often result in poor step coverage, which can result in electrical shorts and/or unwanted inductances, loss of electrode area, or high resistance especially in high aspect trenches or holes.
Another development in the field of thin film technology for coating substrates is atomic layer deposition (ALD). A description of ALD is set forth in U.S. Pat. No. 5,879,459, which is herein incorporated by reference in its entirety. ALD operates by confining a wafer in a reaction chamber at a typical temperature of less than 300 degrees C. Precursor gas is alternatively, nonoverlappingly pulsed into the chamber, wherein the pulsed precursor forms a monolayer on the substrate by chemisorption. The low temperature limits the bonding of the precursor to chemisorption, thus only a single layer, usually only one atom or molecule thick, is grown on the wafer. Each pulse is separated by a purge pulse which completely purges all of the precursor gas from the chamber before the next pulse of precursor gas begins. Each injection of precursor gas provides a new single atomic layer on the previously deposited layers to form a layer of film. Obviously, this significantly increases the time it takes to depose a layer having adequate thickness on the substrate. As a numerical example, ALD has a typical deposition rate of about 100 Å/min and CVD has a typical deposition rate of about 1000 Å/min. For at least this reason, ALD has not met with widespread commercial acceptance.
In light of the foregoing, there is a need for fabrication of thin films which offer improved step coverage and effective fabrication rates.
SUMMARY OF THE INVENTION
The above mentioned problems with thin film fabrication techniques are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for fabricating thin films on substrates. The fabrication technique of the present invention grows more than one atomic layer at a time, improves step coverage and reduces gas phase interactions of the deposition materials such that fewer contaminants are produced.
In one embodiment of the invention, the precursor gas is pulsed into a the deposition chamber and the reactant gas is separately pulsed into the deposition chamber. Another embodiment of the present invention allows a sufficient time to pass after pulsing the precursor gas into a vessel so that the precursor gas is adjacent a substrate and available for deposition thereon.
Additional embodiments of the invention include deposition devices and systems for forming films on substrates, and machine readable media having fabrication instructions stored thereon.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 4058430 (1977-11-01), Suntola et al.
patent: 4413022 (1983-11-01), Suntola et al.
patent: 5102694 (1992-04-01), Taylor et al.
patent: 5138520 (1992-08-01), McMillan et al.
patent: 5146299 (1992-09-01), Lampe et al.
patent: 5164040 (1992-11-

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