Coating processes – Direct application of electrical – magnetic – wave – or... – Pretreatment of substrate or post-treatment of coated substrate
Reexamination Certificate
2002-05-03
2003-05-27
Pianalto, Bernard (Department: 1762)
Coating processes
Direct application of electrical, magnetic, wave, or...
Pretreatment of substrate or post-treatment of coated substrate
C427S123000, C427S250000, C427S255260, C427S255500, C427S294000, C427S570000, C427S576000
Reexamination Certificate
active
06569501
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of advanced thin film deposition methods commonly used in the semiconductor, data storage, flat panel display, as well as allied or other industries. More particularly, the present invention relates to an enhanced sequential or non-sequential atomic layer deposition (ALD) apparatus and technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive thin films.
The disadvantages of conventional ALD are additionally discussed in a copending application with the same assignee entitled “Method and Apparatus for Improved Temperature Control in Atomic Layer Deposition”, which is hereby incorporated by reference in its entirety and may be found as copending application Ser. No. 09/854,092.
2. Brief Description of the Background Art
As integrated circuit (IC) dimensions shrink and the aspect ratios of the resulting features increase, the ability to deposit conformal, ultra-thin films on the sides and bottoms of high aspect ratio trenches and vias becomes increasingly important. These conformal, ultra-thin films are typically used as “liner” material to enhance adhesion, prevent inter-diffusion and/or chemical reaction between the underlying dielectric and the overlying metal, and promote the deposition of a subsequent film.
In addition, decreasing device dimensions and increasing device densities has necessitated the transition from traditional CVD tungsten plug and aluminum interconnect technology to copper interconnect technology. This transition is driven by both the increasing impact of the RC interconnect delay on device speed and by the electromigration (i.e., the mass transport of metal due to momentum transfer between conducting electrons and diffusing metal atoms, thereby affecting reliability) limitations of aluminum based conductors for sub 0.25 &mgr;m device generations. Copper is preferred due to its lower resistivity and higher (greater than 10 times) electromigration resistance as compared to aluminum. A single or dual damascene copper metallization scheme is used since it eliminates the need for copper etching and reduces the number of integration steps required. However, the burden now shifts to the metal deposition step(s) as the copper must fill predefined high aspect ratio trenches and/or vias in the dielectric. Electroplating has emerged as the copper fill technique of choice due to its low deposition temperature, high deposition rate, and potential low manufacturing cost.
Two major challenges exist for copper wiring technology: the barrier and seed layers. Copper can diffuse readily into silicon and most dielectrics. This diffusion may lead to electrical leakage between metal wires and poor device performance. An encapsulating barrier layer is needed to isolate the copper from the surrounding material (e.g., dielectric or Si), thus preventing copper diffusion into and/or reaction with the underlying material (e.g. dielectric or Si). In addition, the barrier layer also serves as the adhesion or glue layer between the patterned dielectric trench or via and the copper used to fill it. The dielectric material can be a low dielectric constant, i.e. low-k material (used to reduce inter- and intra-line capacitance and cross-talk) which typically suffers from poorer adhesion characteristics and lower thermal stability than traditional oxide insulators. Consequently, this places more stringent requirements on the barrier material and deposition method. An inferior adhesion layer will, for example, lead to delamination at either the barrier-to-dielectric or barrier-to-copper interfaces during any subsequent anneal and/or chemical mechanical planarization (CMP) processing steps leading to degradation in device performance and reliability. Ideally, the barrier layer should be thin, conformal, defect free, and of low resistivity so as to not compromise the conductance of the copper metal interconnect structure.
In addition, electroplating fill requires a copper seed layer, which serves to both carry the plating current and act as the nucleation layer. The preferred seed layer should be smooth, continuous, of high purity, and have good step coverage with low overhang. A discontinuity in the seed layer will lead to sidewall voiding, while gross overhang will lead to pinch-off and the formation of top voids.
Both the barrier and seed layers which are critical to successful implementation of copper interconnects require a means of depositing high purity, conformal, ultra-thin films at low substrate temperatures.
Physical vapor deposition (PVD) or sputtering has been adopted as the preferred method of choice for depositing conductor films used in IC manufacturing. This choice has been primarily driven by the low cost, simple sputtering approach whereby relatively pure elemental or compound materials can be deposited at relatively low substrate temperatures. For example, refractory based metals and metal compounds such as tantalum (Ta), tantalum nitride (TaN
x
), other tantalum containing compounds, tungsten (W), tungsten nitride (WN
x
), and other tungsten containing compounds which are used as barrier/adhesion layers can be sputter deposited with the substrate at or near room temperature. However, as device geometries have decreased, the step coverage limitations of PVD have increasingly become an issue since it is inherently a line-of-sight process. This limits the total number of atoms or molecules which can be delivered into the patterned trench or via. As a result, PVD is unable to deposit thin continuous films of adequate thickness to coat the sides and bottoms of high aspect ratio trenches and vias. Moreover, medium/high-density plasma and ionized PVD sources developed to address the more aggressive device structures are still not adequate and are now of such complexity that cost and reliability have become serious concerns.
Chemical vapor deposition (CVD) processes offer improved step coverage since CVD processes can be tailored to provide conformal films. Conformality ensures the deposited films match the shape of the underlying substrate, and the film thickness inside the feature is uniform and equivalent to the thickness outside the feature. Unfortunately, CVD requires comparatively high deposition temperatures, suffers from high impurity concentrations, which impact film integrity, and have higher cost-of-ownership due to long nucleation times and poor precursor gas utilization efficiency. Following the tantalum containing barrier example, CVD Ta and TaN films require substrate temperatures ranging from 500° C. to over 800° C. and suffer from impurity concentrations (typically of carbon and oxygen) ranging from several to tens of atomic % concentration. This generally leads to high film resistivities (up to several orders of magnitude higher than PVD), and other degradation in film performance. These deposition temperatures and impurity concentrations make CVD Ta and TaN unusable for IC manufacturing, in particular for copper metallization and low-k integration.
Chen et al. (“Low temperature plasma-assisted chemical vapor deposition of tantalum nitride from tantalum pentabromide for copper metallization”, J. Vac. Sci. Technol. B 17(1), pp. 182-185 (1999); and “Low temperature plasma-promoted chemical vapor deposition of tantalum from tantalum pentabromide for copper metallization”, J. Vac. Sci. Technol. B 16(5), pp. 2887-2890 (1998)) have demonstrated a plasma-assisted (PACVD) or plasma-enhanced (PECVD) CVD approach using tantalum pentabromide (TaBr
5
) as the precursor gas to reduce the deposition temperature. Ta and TaN
x
films were deposited from 350° C. to 450° C. and contained 2.5 to 3 atomic % concentration of bromine. Although the deposition temperature has been reduced by increased fragmentation (and hence increased reactivity) of the precursor gases in the gas-phase via a plasma, the same fragmentat
Chiang Tony P.
Leeser Karl F.
Angstron Systems, Inc.
Carr & Ferrell LLP
Pianalto Bernard
Scheer Bradley W.
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