Sequential machine for solving boolean satisfiability (SAT)...

Details Sequential machine for solving boolean satisfiability (SAT)... Sequential machine for solving boolean satisfiability (SAT)...

2006-10-10

2006-10-10

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S017000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07120569

ABSTRACT:
The invention is a sequential machine for solving boolean satisfiability (SAT) problems for functions of n variables and m clauses in linear time with complexity O(m), independent of the number of variables in the function. With current hardware technology, a value of n=32 variables can be achieved. The machine can serve as a basic building block to develop faster SAT solvers.

REFERENCES:
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patent: 5831996 (1998-11-01), Abramovici et al.
patent: 6389374 (2002-05-01), Jain et al.
patent: 2004/0210860 (2004-10-01), Ganai et al.
Abramovici, M. and Saab, D., “Satisfiability on Reconfigurable Hardware”, in 7th International Workshop on Field Programmable Logic and Applications (1997).
Cook, S., “The complexity of theorem proving procedures”, Proceedings of the 3rd Annual ACM Symposium on the Theory of Computation (1971) 151-158.
Zhong, P., Martonosi, M., Ashar, P., and Malik, S., .

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